Direct memory access controller (DMA) RM0444
288/1390 RM0444 Rev 5
Bit 17 TCIF5: transfer complete (TC) flag for channel 5
0: no TC event
1: a TC event occurred
Bit 16 GIF5: global interrupt flag for channel 5
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 15 TEIF4: transfer error (TE) flag for channel 4
0: no TE event
1: a TE event occurred
Bit 14 HTIF4: half transfer (HT) flag for channel 4
0: no HT event
1: a HT event occurred
Bit 13 TCIF4: transfer complete (TC) flag for channel 4
0: no TC event
1: a TC event occurred
Bit 12 GIF4: global interrupt flag for channel 4
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 11 TEIF3: transfer error (TE) flag for channel 3
0: no TE event
1: a TE event occurred
Bit 10 HTIF3: half transfer (HT) flag for channel 3
0: no HT event
1: a HT event occurred
Bit 9 TCIF3: transfer complete (TC) flag for channel 3
0: no TC event
1: a TC event occurred
Bit 8 GIF3: global interrupt flag for channel 3
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 7 TEIF2: transfer error (TE) flag for channel 2
0: no TE event
1: a TE event occurred
Bit 6 HTIF2: half transfer (HT) flag for channel 2
0: no HT event
1: a HT event occurred
Bit 5 TCIF2: transfer complete (TC) flag for channel 2
0: no TC event
1: a TC event occurred
Bit 4 GIF2: global interrupt flag for channel 2
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 3 TEIF1: transfer error (TE) flag for channel 1
0: no TE event
1: a TE event occurred
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