ST STM32G0 1 Series

Nested vectored interrupt controller (NVIC) RM0444
316/1390 RM0444 Rev 5
23 30 settable I2C1
I2C1 global interrupt (combined with
EXTI 23)
0x0000_009C
24 31 settable I2C2 / I2C3 I2C2 and I2C3 global interrupt 0x0000_00A0
25 32 settable SPI1 SPI1 global interrupt 0x0000_00A4
26 33 settable SPI2 / SPI3 SPI2 global interrupt 0x0000_00A8
27 34 settable USART1
USART1 global interrupt (combined
with EXTI 25)
0x0000_00AC
28 35 settable USART2 / LPUART2
USART2 and LPUART2 global
interrupt (combined with EXTI 26)
0x0000_00B0
29 36 settable
USART3 / USART4 /
USART5 / USART6 /
LPUART1
USART3/4/5/6 and LPUART1 global
interrupt (combined with EXTI 28)
0x0000_00B4
30 37 settable CEC
CEC global interrupt (combined with
EXTI 27)
0x0000_00B8
31 38 settable AES / RNG AES and RNG global interrupts 0x0000_00BC
1. The grayed cells correspond to the Cortex
®
-M0+ interrupts.
Table 58. Vector table
(1)
(continued)
Position Priority
Type of
priority
Acronym Description Address