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ST STM32G0 1 Series User Manual

ST STM32G0 1 Series
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Contents RM0444
34/1390 RM0444 Rev 5
36 FD controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . 1196
36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196
36.2 FDCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1198
36.3 FDCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1199
36.3.1 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
36.3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
36.3.3 Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
36.3.4 FIFO acknowledge handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
36.3.5 FDCAN Rx FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
36.3.6 FDCAN Tx Buffer element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
36.3.7 FDCAN Tx Event FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
36.3.8 FDCAN Standard message ID Filter element . . . . . . . . . . . . . . . . . . 1225
36.3.9 FDCAN Extended message ID filter element . . . . . . . . . . . . . . . . . . 1226
36.4 FDCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
36.4.1 FDCAN core release register (FDCAN_CREL) . . . . . . . . . . . . . . . . . 1227
36.4.2 FDCAN endian register (FDCAN_ENDN) . . . . . . . . . . . . . . . . . . . . . 1227
36.4.3 FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . 1228
36.4.4 FDCAN test register (FDCAN_TEST) . . . . . . . . . . . . . . . . . . . . . . . . 1229
36.4.5 FDCAN RAM watchdog register (FDCAN_RWD) . . . . . . . . . . . . . . . 1229
36.4.6 FDCAN CC control register (FDCAN_CCCR) . . . . . . . . . . . . . . . . . . 1230
36.4.7 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . 1232
36.4.8 FDCAN timestamp counter configuration register (FDCAN_TSCC) . 1233
36.4.9 FDCAN timestamp counter value register (FDCAN_TSCV) . . . . . . . 1234
36.4.10 FDCAN timeout counter configuration register (FDCAN_TOCC) . . . 1235
36.4.11 FDCAN timeout counter value register (FDCAN_TOCV) . . . . . . . . . 1235
36.4.12 FDCAN error counter register (FDCAN_ECR) . . . . . . . . . . . . . . . . . 1236
36.4.13 FDCAN protocol status register (FDCAN_PSR) . . . . . . . . . . . . . . . . 1236
36.4.14 FDCAN transmitter delay compensation register (FDCAN_TDCR) . . 1239
36.4.15 FDCAN interrupt register (FDCAN_IR) . . . . . . . . . . . . . . . . . . . . . . . 1239
36.4.16 FDCAN interrupt enable register (FDCAN_IE) . . . . . . . . . . . . . . . . . 1242
36.4.17 FDCAN interrupt line select register (FDCAN_ILS) . . . . . . . . . . . . . . 1244
36.4.18 FDCAN interrupt line enable register (FDCAN_ILE) . . . . . . . . . . . . . 1245
36.4.19 FDCAN global filter configuration register (FDCAN_RXGFC) . . . . . . 1245
36.4.20 FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . . . . . 1247
36.4.21 FDCAN high-priority message status register (FDCAN_HPMS) . . . . 1247
36.4.22 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . . . . . . . . . 1248

Table of Contents

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ST STM32G0 1 Series Specifications

General IconGeneral
BrandST
ModelSTM32G0 1 Series
CategoryMicrocontrollers
LanguageEnglish

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