ST STM32G0 1 Series User Manual

RM0444 Rev 5 35/1390
RM0444 Contents
38
36.4.23 CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . . . . . . 1249
36.4.24 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . . . . . . . . . 1249
36.4.25 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . . . 1250
36.4.26 FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . . . . . . 1250
36.4.27 FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . . . . . 1251
36.4.28 FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . . 1252
36.4.29 FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . . . . . . 1253
36.4.30 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . 1253
36.4.31 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) 1254
36.4.32 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . 1254
36.4.33 FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
36.4.34 FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_ TXBCIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
36.4.35 FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . . . . . . 1256
36.4.36 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . 1256
36.4.37 FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . . . . . . . . . 1257
36.4.38 FDCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
37 Universal serial bus full-speed host/device interface (USB) . . . . . . 1262
37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
37.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
37.3 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
37.4 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
37.4.1 Description of USB blocks used in both Device and Host modes . . . 1265
37.4.2 Description of host frame scheduler (HFS) specific to Host mode . . 1266
37.5 Programming considerations for Device and Host modes . . . . . . . . . . 1267
37.5.1 Generic USB Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
37.5.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
37.5.3 Double-buffered endpoints and usage in Device mode . . . . . . . . . . . 1274
37.5.4 Double buffered channels: usage in Host mode . . . . . . . . . . . . . . . . 1276
37.5.5 Isochronous transfers in Device mode . . . . . . . . . . . . . . . . . . . . . . . 1277
37.5.6 Isochronous transfers in Host mode . . . . . . . . . . . . . . . . . . . . . . . . . 1279
37.5.7 Suspend/resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
37.6 USB and USB SRAM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
37.6.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
37.6.2 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English