RM0444 Rev 5 621/1390
RM0444 Advanced-control timer (TIM1)
624
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 TI3SEL[3:0]: selects TI3[0] to TI3[15] input
0000: TIM1_CH3 input
0001: COMP3 output (available on STM32G0B1xx and STM32G0C1xx salestypes only)
Others: Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 TI2SEL[3:0]: selects TI2[0] to TI2[15] input
0000: TIM1_CH2 input
0001: COMP2 output
Others: Reserved
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
0000: TIM1_CH1 input
0001: COMP1 output
Others: Reserved
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