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ST STM32G0 1 Series

ST STM32G0 1 Series
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General-purpose timers (TIM15/TIM16/TIM17) RM0444
774/1390 RM0444 Rev 5
the counter value and a potential roll-over condition signaled by the UIFCPY flag, to be
atomically read. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.

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