Embedded Flash memory (FLASH) RM0444
82/1390 RM0444 Rev 5
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 IRHEN: Internal reset holder enable bit
0: Internal resets are propagated as simple pulse on NRST pin
1: Internal resets drives NRST pin low until it is seen as low level
Bits 28: 27 NRST_MODE[1:0]
00: Reserved
01: Reset Input only: a low level on the NRST pin generates system reset, internal RESET
not propagated to the NSRT pin
10: GPIO: standard GPIO pad functionality, only internal RESET possible
11: Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
Bit 26 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 25 nBOOT1: Boot configuration
Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit
configuration), this bit selects boot mode from the Main Flash memory, SRAM or the
System memory. Refer to Section 2.5: Boot configuration.
Bit 24 nBOOT_SEL: BOOT0 signal source selection
This option bit defines the source of the BOOT0 signal.
0: BOOT0 pin (legacy mode)
1: nBOOT0 option bit
Bit 23 Reserved, must be kept at reset value.
Bit 22 RAM_PARITY_CHECK: SRAM parity check control enable
0: Enable
1: Disable
Bit 21 DUAL_BANK: Dual-bank on 512 Kbytes or 256 Kbytes Flash memory devices
0: 256 Kbytes/512 Kbytes single-bank Flash memory, contiguous addresses in Bank 1
1: 256 Kbytes/512 Kbytes dual-bank Flash memory, Refer to Table 10 and Tabl e 11
Bit 20 nSWAP_BANK: Empty check boot configuration
This bit selects the bank that is the subject of empty check upon boot.
0: Bank 1
1: Bank 2
This bit pertains to dual-bank devices only. In single-bank devices, it is reserved.
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IDWG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
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