DocID024597 Rev 3 1689/1693
RM0351 Revision history
1692
15-Oct-2015
2
(continued)
I2C
Updated Section 35.4.4: I2C initialization, including
Figure 354: Setup and hold timings.
Updated Section 35.7.5: Timing register
(I2C_TIMINGR).
SPI
Updated Figure 421, Figure 422, Figure 423 and
Figure 424.
Notes updated and added below Figure 421,
Figure 422, Figure 423.
Added Section 38.4.4: Multi-master communication.
UART
Updated Note:.
Added Section : Determining the maximum USART
baudrate allowing to wakeup correctly from stop mode
when the USART clock source is the HSI clock.
Removed TXFRQ bit in Table 204: LPUART register
map and reset values.
DEBUG
Updated Section : DBGMCU_IDCODE.
08-Dec-2015 3
In all the document:
– Stop 1 with main regulator becomes Stop 0
– Stop 1 with low-power regulator remains as Stop 1
MEM
Updated SAI1 and SAI2 base address in Tab le 1:
STM32L4x6 memory map and peripheral register
boundary addresses.
MMAP
Added Table 4: Memory mapping versus boot
mode/physical remap.
FLASH
Added Note: in Section : Fast programming.
PWR
Updated Table 20: Functionalities depending on the
working mode.
RCC
Updated WWDGEN bit description and access mode in
Section 6.4.19: APB1 peripheral clock enable register 1
(RCC_APB1ENR1).
NVIC
Updated Figure 27: External interrupt/event GPIO
mapping.
Updated reset value in Section 12.5.7: Interrupt mask
register 2 (EXTI_IMR2).
Table 281. Document revision history (continued)
Date Revision Changes