ST STM32L4x6 User Manual

Revision history RM0351
1690/1693 DocID024597 Rev 3
08-Dec-2015
3
(continued)
FMC
Updated BUSTURN bit description in Section :
SRAM/NOR-Flash chip-select timing registers 1..4
(FMC_BTR1..4).
ADC
Updated VDDA in Table 85: ADC pins.
DAC
Added Section : Example of the sample and refresh time
calculation with output buffer on.
Updated Table 105: Effect of low-power modes on DAC.
COMP
Updated Table 113: Comparator behavior in the low
power modes.
OPAMP
Updated Table 118: Effect of low-power modes on the
OPAMP.
Added Note.
LCD
Updated Table 131: LCD behavior in low-power modes.
TSC
Added note in Section 23.3.4: Charge transfer
acquisition sequence.
Updated Table 137: Effect of low-power modes on TSC.
Added notes in CTPL and PGPSC bit description in
Section 23.6.1: TSC control register (TSC_CR).
TIM1/TIM8
Updated Section 26.3.21: Retriggerable one pulse mode
(OPM).
Updated SMS bit description in Section 26.4.3:
TIM1/TIM8 slave mode control register (TIMx_SMCR).
Updated reset value to 0xFFFF in Section 26.4.12:
TIM1/TIM8 auto-reload register (TIMx_ARR).
TIM2/TIM3/TIM4/TIM5
Added Section 27.3.14: Retriggerable one pulse mode
(OPM).
Updated SMS bitfield description in Section 27.4.3: TIMx
slave mode control register (TIMx_SMCR).
Updated CC1IF bit description in Section 27.4.5: TIMx
status register (TIMx_SR).
Updated reset value to 0xFFFF in Section 27.4.12: TIMx
auto-reload register (TIMx_ARR).
TIM15/TIM16/TIM17
Updated Section 28.4.17: External trigger
synchronization (TIM15 only).
Removed bit CC2NE from Section 28.5.8: TIM15
capture/compare enable register (TIM15_CCER).
Removed bit TIE from Section 28.6.3: TIM16&TIM17
DMA/interrupt enable register (TIMx_DIER).
Table 281. Document revision history (continued)
Date Revision Changes

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English