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NXP Semiconductors LPC1768 - Page 812

NXP Semiconductors LPC1768
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UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 812 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
(STCTRL - 0xE000 E010) bit description . . .506
Table 440. System Timer Reload value register (STRELOAD
- 0xE000 E014) bit description . . . . . . . . . . . .507
Table 441. System Timer Current value register (STCURR -
0xE000 E018) bit description . . . . . . . . . . . . .507
Table 442. System Timer Calibration value register
(STCALIB - 0xE000 E01C) bit description . . .508
Table 443. Set and reset inputs for PWM Flip-Flops . . . .513
Table 444. Pin summary . . . . . . . . . . . . . . . . . . . . . . . . .514
Table 445. PWM1 register map . . . . . . . . . . . . . . . . . . .515
Table 446: PWM Interrupt Register (PWM1IR - address
0x4001 8000) bit description . . . . . . . . . . . . .516
Table 447. PWM Timer Control Register (PWM1TCR
address 0x4001 8004) bit description. . . . . . .517
Table 448. PWM Count control Register (PWM1CTCR -
address 0x4001 8070) bit description. . . . . . .518
Table 449: Match Control Register (PWM1MCR - address
0x4001 8014) bit description . . . . . . . . . . . . .518
Table 450: PWM Capture Control Register (PWM1CCR -
address 0x4001 8028) bit description. . . . . . .520
Table 451: PWM Control Register (PWM1PCR - address
0x4001 804C) bit description . . . . . . . . . . . . .520
Table 452: PWM Latch Enable Register (PWM1LER -
address 0x4001 8050) bit description. . . . . . .522
Table 453. Pin summary . . . . . . . . . . . . . . . . . . . . . . . . .523
Table 454. Motor Control Pulse Width Modulator (MCPWM)
register map . . . . . . . . . . . . . . . . . . . . . . . . . .526
Table 455. MCPWM Control read address (MCCON -
0x400B 8000) bit description . . . . . . . . . . . . .527
Table 456. MCPWM Control set address (MCCON_SET -
0x400B 8004) bit description . . . . . . . . . . . . .528
Table 457. MCPWM Control clear address (MCCON_CLR -
0x400B 8008) bit description . . . . . . . . . . . . .529
Table 458. MCPWM Capture Control read address
(MCCAPCON - 0x400B 800C) bit description 529
Table 459. MCPWM Capture Control set address
(MCCAPCON_SET - 0x400B 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530
Table 460. MCPWM Capture control clear register
(MCCAPCON_CLR - address 0x400B 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530
Table 461. Motor Control PWM interrupts . . . . . . . . . . . .530
Table 462. Interrupt sources bit allocation table . . . . . . .530
Table 463. MCPWM Interrupt Enable read address
(MCINTEN - 0x400B 8050) bit description . . .530
Table 464. PWM interrupt enable set register
(MCINTEN_SET - address 0x400B 8054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .531
Table 465. PWM interrupt enable clear register
(MCINTEN_CLR - address 0x400B 8058) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .531
Table 466. MCPWM Interrupt Flags read address (MCINTF -
0x400B 8068) bit description . . . . . . . . . . . . .531
Table 467. MCPWM Interrupt Flags set address
(PWMINTF_SET - 0x400B 806C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .531
Table 468. MCPWM Interrupt Flags clear address
(PWMINTF_CLR - 0x400B 8070) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Table 469. MCPWM Count Control read address
(MCCNTCON - 0x400B 805C) bit description 532
Table 470. MCPWM Count Control set address
(MCCNTCON_SET - 0x400B 8060) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Table 471. MCPWM Count Control clear address
(MCCAPCON_CLR - 0x400B 8064) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2
- 0x400B 8018, 0x400B 801C, 0x400B 8020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Table 473. MCPWM Limit 0-2 registers (MCLIM0-2 -
0x400B 8024, 0x400B 8028, 0x400B 802C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Table 474. MCPWM Match 0-2 registers (MCMAT0-2 -
addresses 0x400B 8030, 0x400B 8034,
0x400B 8038) bit description . . . . . . . . . . . . . 535
Table 475. MCPWM Dead-time register (MCDT - address
0x400B 803C) bit description. . . . . . . . . . . . . 536
Table 476. MCPWM Commutation Pattern register (MCCP -
address 0x400B 8040) bit description . . . . . . 536
Table 477. MCPWM Capture read addresses (MCCAP0/1/2
- 0x400B 8044, 0x400B 8048, 0x400B 804C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Table 478. MCPWM Capture clear address (CAP_CLR -
0x400B 8074) bit description . . . . . . . . . . . . . 537
Table 479. Encoder states . . . . . . . . . . . . . . . . . . . . . . . 546
Table 480. Encoder state transitions
[1]
. . . . . . . . . . . . . . 546
Table 481. Encoder direction . . . . . . . . . . . . . . . . . . . . . 547
Table 482. QEI pin description . . . . . . . . . . . . . . . . . . . . 549
Table 483. QEI Register summary . . . . . . . . . . . . . . . . . 550
Table 484: QEI Control register (QEICON - address
0x400B C000) bit description. . . . . . . . . . . . . 551
Table 485: QEI Configuration register (QEICONF - address
0x400B C008) bit description. . . . . . . . . . . . . 551
Table 486: QEI Interrupt Status register (QEISTAT - address
0x400B C004) bit description. . . . . . . . . . . . . 551
Table 487: QEI Position register (QEIPOS - address
0x400B C00C) bit description . . . . . . . . . . . . 552
Table 488: QEI Maximum Position register (QEIMAXPOS -
address 0x400B C010) bit description. . . . . . 552
Table 489: QEI Position Compare register 0 (CMPOS0 -
address 0x400B C014) bit description. . . . . . 552
Table 490: QEI Position Compare register 1 (CMPOS1 -
address 0x400B C018) bit description. . . . . . 552
Table 491: QEI Position Compare register 2 (CMPOS2 -
address 0x400B C01C) bit description . . . . . 553
Table 492: QEI Index Count register (INXCNT - address
0x400B C020) bit description. . . . . . . . . . . . . 553
Table 493: QEI Index Compare register (INXCMP - address
0x400B C024) bit description. . . . . . . . . . . . . 553
Table 494: QEI Timer Load register (QEILOAD - address
0x400B C028) bit description. . . . . . . . . . . . . 553
Table 495: QEI Timer register (QEITIME - address
0x400B C02C) bit description . . . . . . . . . . . . 554
Table 496: QEI Velocity register (QEIVEL - address
0x400B C030) bit description. . . . . . . . . . . . . 554

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