UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 813 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
Table 497: QEI Velocity Capture register (QEICAP - address
0x400B C034) bit description . . . . . . . . . . . . .554
Table 498: QEI Velocity Compare register (VELCOMP -
address 0x400B C038) bit description . . . . . .554
Table 499: QEI Digital Filter register (FILTER - address
0x400B C03C) bit description. . . . . . . . . . . . .554
Table 500: QEI Interrupt Status register (QEIINTSTAT -
address 0x400B CFE0) bit description . . . . . .555
Table 501: QEI Interrupt Set register (QEISET - address
0x400B CFEC) bit description . . . . . . . . . . . .555
Table 502: QEI Interrupt Clear register (QEICLR -
0x400B CFE8) bit description. . . . . . . . . . . . .556
Table 503: QEI Interrupt Enable register (QEIIE - address
0x400B CFE4) bit description . . . . . . . . . . . .556
Table 504: QEI Interrupt Enable Set register (QEIIES -
address 0x400B CFDC) bit description . . . . .557
Table 505: QEI Interrupt Enable Clear register (QEIIEC -
address 0x400B CFD8) bit description. . . . . .558
Table 506. RTC pin description . . . . . . . . . . . . . . . . . . . .561
Table 507. Real-Time Clock register map . . . . . . . . . . . .562
Table 508. Interrupt Location Register (ILR - address
0x4002 4000) bit description . . . . . . . . . . . . .563
Table 509. Clock Control Register (CCR - address
0x4002 4008) bit description . . . . . . . . . . . . .563
Table 510. Counter Increment Interrupt Register (CIIR -
address 0x4002 400C) bit description . . . . . .564
Table 511. Alarm Mask Register (AMR - address
0x4002 4010) bit description . . . . . . . . . . . . .565
Table 512. RTC Auxiliary control register (RTC_AUX -
address 0x4002 405C) bit description . . . . . .565
Table 513. RTC Auxiliary Enable register (RTC_AUXEN -
address 0x4002 4058) bit description. . . . . . .565
Table 514. Consolidated Time register 0 (CTIME0 - address
0x4002 4014) bit description . . . . . . . . . . . . .566
Table 515. Consolidated Time register 1 (CTIME1 - address
0x4002 4018) bit description . . . . . . . . . . . . .566
Table 516. Consolidated Time register 2 (CTIME2 - address
0x4002 401C) bit description . . . . . . . . . . . . .567
Table 517. Time Counter relationships and values . . . . .567
Table 518. Time Counter registers . . . . . . . . . . . . . . . . .567
Table 519. Calibration register (CALIBRATION - address
0x4002 4040) bit description . . . . . . . . . . . . .568
Table 520. General purpose registers 0 to 4 (GPREG0 to
GPREG4 - addresses 0x4002 4044 to 0x4002
4054) bit description . . . . . . . . . . . . . . . . . . . .569
Table 521. Alarm registers. . . . . . . . . . . . . . . . . . . . . . . .569
Table 522. Watchdog register map . . . . . . . . . . . . . . . . .571
Table 523: Watchdog Mode register (WDMOD, address
0x4000 0000) bit description . . . . . . . . . . . . .572
Table 524. Watchdog operating modes selection . . . . . .572
Table 525: Watchdog Constant register (WDTC, address
0x4000 0004) bit description . . . . . . . . . . . . .573
Table 526: Watchdog Feed register (WDFEED, address
0x4000 0008) bit description . . . . . . . . . . . . .573
Table 527: Watchdog Timer Value register (WDTV, address
0x4000 000C) bit description . . . . . . . . . . . . .573
Table 528: Watchdog Timer Clock Source Selection register
(WDCLKSEL, address 0x4000 0010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Table 529. ADC pin description . . . . . . . . . . . . . . . . . . . 576
Table 530. ADC registers . . . . . . . . . . . . . . . . . . . . . . . . 577
Table 531: A/D Control Register (AD0CR - address
0x4003 4000) bit description . . . . . . . . . . . . . 578
Table 532: A/D Global Data Register (AD0GDR - address
0x4003 4004) bit description . . . . . . . . . . . . . 579
Table 533: A/D Interrupt Enable register (AD0INTEN -
address 0x4003 400C) bit description . . . . . 579
Table 534: A/D Data Registers (AD0DR0 to AD0DR7 -
0x4003 4010 to 0x4003 402C) bit description 580
Table 535: A/D Status register (AD0STAT - address
0x4003 4030) bit description . . . . . . . . . . . . . 581
Table 536: A/D Trim register (ADTRM - address
0x4003 4034) bit description . . . . . . . . . . . . . 581
Table 537. D/A Pin Description. . . . . . . . . . . . . . . . . . . . 583
Table 538. DAC registers . . . . . . . . . . . . . . . . . . . . . . . . 584
Table 539: D/A Converter Register (DACR - address
0x4008 C000) bit description . . . . . . . . . . . . . 584
Table 540. D/A Control register (DACCTRL - address
0x4008 C004) bit description . . . . . . . . . . . . . 585
Table 541: D/A Converter register (DACR - address
0x4008 C008) bit description . . . . . . . . . . . . . 585
Table 542. Endian behavior . . . . . . . . . . . . . . . . . . . . . . 590
Table 543. DMA Connections . . . . . . . . . . . . . . . . . . . . . 593
Table 544. GPDMA register map . . . . . . . . . . . . . . . . . . 594
Table 545. DMA Interrupt Status register (DMACIntStat -
0x5000 4000) . . . . . . . . . . . . . . . . . . . . . . . . 596
Table 546. DMA Interrupt Terminal Count Request Status
register (DMACIntTCStat - 0x5000 4004) . . . 596
Table 547. DMA Interrupt Terminal Count Request Clear
register (DMACIntTCClear - 0x5000 4008) . . 596
Table 548. DMA Interrupt Error Status register
(DMACIntErrStat - 0x5000 400C) . . . . . . . . . 597
Table 549. DMA Interrupt Error Clear register
(DMACIntErrClr - 0x5000 4010) . . . . . . . . . . 597
Table 550. DMA Raw Interrupt Terminal Count Status
register (DMACRawIntTCStat - 0x5000
4014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Table 551. DMA Raw Error Interrupt Status register
(DMACRawIntErrStat - 0x5000 4018) . . . . . . 598
Table 552. DMA Enabled Channel register
(DMACEnbldChns - 0x5000 401C) . . . . . . . . 598
Table 553. DMA Software Burst Request register
(DMACSoftBReq - 0x5000 4020) . . . . . . . . . 598
Table 554. DMA Software Single Request register
(DMACSoftSReq - 0x5000 4024) . . . . . . . . . 599
Table 555. DMA Software Last Burst Request register
(DMACSoftLBReq - 0x5000 4028) . . . . . . . . 599
Table 556. DMA Software Last Single Request register
(DMACSof
t
LSReq - 0x5000 402C) . . . . . . . . 600
Table 557. DMA Configuration register (DMACConfig -
0x5000 4030) . . . . . . . . . . . . . . . . . . . . . . . . 600
Table 558. DMA Synchronization register (DMACSync -
0x5000 4034) . . . . . . . . . . . . . . . . . . . . . . . . 600
Table 559. DMA Request Select register (DMAReqSel -
0x400F C1C4) . . . . . . . . . . . . . . . . . . . . . . . . 601
Table 560. DMA Channel Source Address registers
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