UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 814 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
(DMACCxSrcAddr - 0x5000 41x0) . . . . . . . . .602
Table 561. DMA Channel Destination Address registers
(DMACCxDestAddr - 0x5000 41x4) . . . . . . . .602
Table 562. DMA Channel Linked List Item registers
(DMACCxLLI - 0x5000 41x8) . . . . . . . . . . . . .603
Table 563. DMA channel control registers (DMACCxControl
- 0x5000 41xC) . . . . . . . . . . . . . . . . . . . . . . .604
Table 564. DMA Channel Configuration registers
(DMACCxConfig - 0x5000 41x0) . . . . . . . . . .606
Table 565. Transfer type bits . . . . . . . . . . . . . . . . . . . . .607
Table 566. DMA request signal usage . . . . . . . . . . . . . .610
Table 567. Sectors in a LPC176x/5x device . . . . . . . . . .621
Table 568. Code Read Protection options
[1]
. . . . . . . . . .622
Table 569. Code Read Protection hardware/software
interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . .623
Table 570. ISP command summary. . . . . . . . . . . . . . . . .624
Table 571. ISP Unlock command . . . . . . . . . . . . . . . . . .624
Table 572. ISP Set Baud Rate command . . . . . . . . . . . .625
Table 573. Correlation between possible ISP baudrates and
CCLK frequency (in MHz). . . . . . . . . . . . . . . .625
Table 574. ISP Echo command. . . . . . . . . . . . . . . . . . . .625
Table 575. ISP Write to RAM command . . . . . . . . . . . . .626
Table 576. ISP Read Memory command. . . . . . . . . . . . .626
Table 577. ISP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .627
Table 578. ISP Copy command. . . . . . . . . . . . . . . . . . . .627
Table 579. ISP Go command. . . . . . . . . . . . . . . . . . . . . .628
Table 580. ISP Erase sector command. . . . . . . . . . . . . .628
Table 581. ISP Blank check sector command. . . . . . . . .629
Table 582. ISP Read Part Identification command . . . . .629
Table 583. LPC176x/5x part identification numbers . . . .629
Table 584. ISP Read Boot Code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .630
Table 585. ISP Read device serial number command. . .630
Table 586. ISP Compare command. . . . . . . . . . . . . . . . .630
Table 587. ISP Return Codes Summary . . . . . . . . . . . . .631
Table 588. IAP Command Summary. . . . . . . . . . . . . . . .633
Table 589. IAP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .634
Table 590. IAP Copy RAM to Flash command . . . . . . . .635
Table 591. IAP Erase Sector(s) command . . . . . . . . . . .635
Table 592. IAP Blank check sector(s) command. . . . . . .636
Table 593. IAP Read part identification number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .636
Table 594. IAP Read Boot Code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .636
Table 595. IAP Read device serial number command. . .637
Table 596. IAP Compare command. . . . . . . . . . . . . . . . .637
Table 597. Re-invoke ISP . . . . . . . . . . . . . . . . . . . . . . . .637
Table 598. IAP Status Codes Summary . . . . . . . . . . . . .638
Table 599. Register overview: FMC (base address 0x4008
4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639
Table 600. Flash Module Signature Start register
(FMSSTART - 0x4008 4020) bit description. .640
Table 601. Flash Module Signature Stop register (FMSSTOP
- 0x4008 4024) bit description . . . . . . . . . . . .640
Table 602. FMSW0 register bit description (FMSW0,
address: 0x4008 402C) . . . . . . . . . . . . . . . . .640
Table 603. FMSW1 register bit description (FMSW1,
address: 0x4008 4030) . . . . . . . . . . . . . . . . . 640
Table 604. FMSW2 register bit description (FMSW2,
address: 0x4008 4034) . . . . . . . . . . . . . . . . . 641
Table 605. FMSW3 register bit description (FMSW3,
address: 0x4008 4038) . . . . . . . . . . . . . . . . 641
Table 606. Flash module Status register (FMSTAT - 0x4008
4FE0) bit description . . . . . . . . . . . . . . . . . . . 641
Table 607. Flash Module Status Clear register (FMSTATCLR
- 0x0x4008 4FE8) bit description . . . . . . . . . . 641
Table 608. JTAG pin description. . . . . . . . . . . . . . . . . . . 644
Table 609. Serial Wire Debug pin description. . . . . . . . . 644
Table 610. Parallel Trace pin description . . . . . . . . . . . . 644
Table 611. Memory Mapping Control register (MEMMAP -
0x400F C040) bit description. . . . . . . . . . . . . 645
Table 612. Cortex-M3 instructions . . . . . . . . . . . . . . . . 649
Table 613. CMSIS intrinsic functions to generate some
Cortex-M3 instructions. . . . . . . . . . . . . . . . . . 652
Table 614. CMSIS intrinsic functions to access the special
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
Table 615. Condition code suffixes . . . . . . . . . . . . . . . . . 659
Table 616. Memory access instructions . . . . . . . . . . . . . 661
Table 617. Offset ranges. . . . . . . . . . . . . . . . . . . . . . . . . 664
Table 618. Offset ranges. . . . . . . . . . . . . . . . . . . . . . . . . 670
Table 619. Data processing instructions. . . . . . . . . . . . . 678
Table 620. Multiply and divide instructions . . . . . . . . . . . 693
Table 621. Packing and unpacking instructions . . . . . . . 701
Table 622. Branch and control instructions. . . . . . . . . . . 706
Table 623. Branch ranges. . . . . . . . . . . . . . . . . . . . . . . . 707
Table 624. Miscellaneous instructions . . . . . . . . . . . . . . 715
Table 625. Summary of processor mode, execution privilege
level, and stack use options. . . . . . . . . . . . . . 729
Table 626. Core register set summary . . . . . . . . . . . . . . 729
Table 627. PSR register combinations . . . . . . . . . . . . . . 731
Table 628. APSR bit assignments . . . . . . . . . . . . . . . . . 732
Table 629. IPSR bit assignments . . . . . . . . . . . . . . . . . . 733
Table 630. EPSR bit assignments . . . . . . . . . . . . . . . . . 733
Table 631. PRIMASK register bit assignments . . . . . . . . 734
Table 632. FAULTMASK register bit assignments . . . . . 734
Table 633. BASEPRI register bit assignments . . . . . . . . 735
Table 634. CONTROL register bit assignments . . . . . . . 735
Table 635. Memory access behavior . . . . . . . . . . . . . . . 739
Table 636. SRAM memory bit-banding regions . . . . . . . 741
Table 637. Peripheral memory bit-banding regions . . . . 741
Table 638. C compiler intrinsic functions for exclusive access
instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Table 639. Properties of the different exception types . . 747
Table 640. Exception return behavior . . . . . . . . . . . . . . 752
Table 641. Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Table 642. Fault status and fault address registers . . . . 755
Table 643. Core peripheral register regions . . . . . . . . . . 760
Table 644. NVIC register summary. . . . . . . . . . . . . . . . . 761
Table 645. Mapping of interrupts to the interrupt
variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Table 646. ISER bit assignments . . . . . . . . . . . . . . . . . . 762
Table 647. ICER bit assignments . . . . . . . . . . . . . . . . . . 763
Table 648. ISPR bit assignments . . . . . . . . . . . . . . . . . . 763
Table 649. ICPR bit assignments . . . . . . . . . . . . . . . . . . 764
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