UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 811 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
description . . . . . . . . . . . . . . . . . . . . . . . . . . .443
Table 386. I
2
C Status register (I2STAT: I
2
C0, I2C0STAT -
0x4001 C004; I
2
C1, I2C1STAT - 0x4005 C004;
I
2
C2, I2C2STAT - 0x400A 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .444
Table 387. I
2
C Data register (I2DAT: I
2
C0, I2C0DAT -
0x4001 C008; I
2
C1, I2C1DAT - 0x4005 C008;
I
2
C2, I2C2DAT - 0x400A 0008) bit description445
Table 388. I
2
C Monitor mode control register (I2MMCTRL:
I
2
C0, I2C0MMCTRL - 0x4001 C01C; I
2
C1,
I2C1MMCTRL- 0x4005 C01C; I
2
C2,
I2C2MMCTRL- 0x400A 001C) bit description 445
Table 389. I
2
C Data buffer register (I2DATA_BUFFER: I
2
C0,
I2CDATA_BUFFER - 0x4001 C02C; I
2
C1,
I2C1DATA_BUFFER- 0x4005 C02C; I
2
C2,
I2C2DATA_BUFFER- 0x400A 002C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .447
Table 390. I
2
C Slave Address registers (I2ADR0 to 3: I
2
C0,
I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28];
I
2
C1, I2C1ADR[0, 1, 2, 3] - address
0x4005 C0[0C, 20, 24, 28]; I
2
C2, I2C2ADR[0, 1, 2,
3] - address 0x400A 00[0C, 20, 24, 28]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .447
Table 391. I
2
C Mask registers (I2MASK0 to 3: I
2
C0,
I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C];
I
2
C1, I2C1MASK[0, 1, 2, 3] - address
0x4005 C0[30, 34, 38, 3C]; I
2
C2, I2C2MASK[0, 1,
2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .448
Table 392. I
2
C SCL HIGH Duty Cycle register (I2SCLH: I
2
C0,
I2C0SCLH - address 0x4001 C010; I
2
C1,
I2C1SCLH - address 0x4005 C010; I
2
C2,
I2C2SCLH - 0x400A 0010) bit description . . .448
Table 393. I
2
C SCL Low duty cycle register (I2SCLL: I
2
C0 -
I2C0SCLL: 0x4001 C014; I
2
C1 - I2C1SCLL:
0x4005 C014; I
2
C2 - I2C2SCLL: 0x400A 0014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .448
Table 394. Example I
2
C clock rates. . . . . . . . . . . . . . . . .449
Table 395. Abbreviations used to describe an I
2
C
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
Table 396. I2CONSET used to initialize Master Transmitter
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
Table 397. I2CONSET used to initialize Slave Receiver
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455
Table 398. Master Transmitter mode. . . . . . . . . . . . . . . .458
Table 399. Master Receiver mode. . . . . . . . . . . . . . . . . .459
Table 400. Slave Receiver mode. . . . . . . . . . . . . . . . . . .460
Table 401. Slave Transmitter mode. . . . . . . . . . . . . . . . .462
Table 402. Miscellaneous States . . . . . . . . . . . . . . . . . . .463
Table 403. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . .476
Table 404. I2S register map. . . . . . . . . . . . . . . . . . . . . . .477
Table 405: Digital Audio Output register (I2SDAO - address
0x400A 8000) bit description . . . . . . . . . . . . .477
Table 406: Digital Audio Input register (I2SDAI - address
0x400A 8004) bit description . . . . . . . . . . . . .478
Table 407: Transmit FIFO register (I2STXFIFO - address
0x400A 8008) bit description . . . . . . . . . . . . .478
Table 408: Receive FIFO register (I2RXFIFO - address
0x400A 800C) bit description. . . . . . . . . . . . . 479
Table 409: Status Feedback register (I2SSTATE - address
0x400A 8010) bit description . . . . . . . . . . . . . 479
Table 410: DMA Configuration register 1 (I2SDMA1 -
address 0x400A 8014) bit description . . . . . . 479
Table 411: DMA Configuration register 2 (I2SDMA2 -
address 0x400A 8018) bit description . . . . . . 480
Table 412: Interrupt Request Control register (I2SIRQ -
address 0x400A 801C) bit description. . . . . . 480
Table 413: Transmit Clock Rate register (I2TXRATE -
address 0x400A 8020) bit description . . . . . . 481
Table 414: Receive Clock Rate register (I2SRXRATE -
address 0x400A 8024) bit description . . . . . . 482
Table 415: Transmit Clock Rate register (I2TXBITRATE -
address 0x400A 8028) bit description . . . . . . 482
Table 416: Receive Clock Rate register (I2SRXBITRATE -
address 0x400A 802C) bit description. . . . . . 482
Table 417: Transmit Mode Control register (I2STXMODE -
0x400A 8030) bit description . . . . . . . . . . . . . 483
Table 418: Receive Mode Control register (I2SRXMODE -
0x400A 8034) bit description . . . . . . . . . . . . . 483
Table 419: I2S transmit modes . . . . . . . . . . . . . . . . . . . . 485
Table 420: I2S receive modes . . . . . . . . . . . . . . . . . . . . 487
Table 421. Conditions for FIFO level comparison. . . . . . 489
Table 422. DMA and interrupt request generation . . . . . 489
Table 423. Status feedback in the I2SSTATE register . . 489
Table 424. Timer/Counter pin description . . . . . . . . . . . . 492
Table 425. TIMER/COUNTER0-3 register map . . . . . . . 493
Table 426. Interrupt Register (T[0/1/2/3]IR - addresses
0x4000 4000, 0x4000 8000, 0x4009 0000,
0x4009 4000) bit description . . . . . . . . . . . . . 494
Table 427. Timer Control Register (TCR, TIMERn: TnTCR -
addresses 0x4000 4004, 0x4000 8004,
0x4009 0004, 0x4009 4004) bit description . . 495
Table 428. Count Control Register (T[0/1/2/3]CTCR -
addresses 0x4000 4070, 0x4000 8070,
0x4009 0070, 0x4009 4070) bit description . 495
Table 429. Match Control Register (T[0/1/2/3]MCR -
addresses 0x4000 4014, 0x4000 8014,
0x4009 0014, 0x4009 4014) bit description . . 497
Table 430. Capture Control Register (T[0/1/2/3]CCR -
addresses 0x4000 4028, 0x4000 8020,
0x4009 0028, 0x4009 4028) bit description . . 498
Table 431. External Match Register (T[0/1/2/3]EMR -
addresses 0x4000 403C, 0x4000 803C,
0x4009 003C, 0x4009 403C) bit description . 499
Table 432. External Match Control . . . . . . . . . . . . . . . . . 499
Table 433. Repetitive Interrupt Timer register map. . . . . 502
Table 434. RI Compare Value register (RICOMPVAL -
address 0x400B 0000) bit description . . . . . . 502
Table 435. RI Mask register (RIMASK - address 0x400B
0004) bit description. . . . . . . . . . . . . . . . . . . . 502
Table 436. RI Control register (RICTRL - address 0x400B
0008) bit description. . . . . . . . . . . . . . . . . . . . 503
Table 437. RI Counter register (RICOUNTER - address
0x400B 000C) bit description. . . . . . . . . . . . . 503
Table 438. System Tick Timer register map . . . . . . . . . . 506
Table 439. System Timer Control and status register
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