UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 810 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
Table 333. CAN Transmit Data register A (CAN1TDA[1/2/3] -
address 0x4004 40[38/48/58], CAN2TDA[1/2/3] -
address 0x4004 80[38/48/58]) bit description.370
Table 334. CAN Transmit Data register B (CAN1TDB[1/2/3] -
address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] -
address 0x4004 80[3C/4C/5C]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .370
Table 335. CAN Sleep Clear register (CANSLEEPCLR -
address 0x400F C110) bit description . . . . . .370
Table 336. CAN Wake-up Flags register (CANWAKEFLAGS
- address 0x400F C114) bit description . . . . .371
Table 337. Central Transit Status Register (CANTxSR -
address 0x4004 0000) bit description. . . . . . .373
Table 338. Central Receive Status Register (CANRxSR -
address 0x4004 0004) bit description. . . . . . .373
Table 339. Central Miscellaneous Status Register (CANMSR
- address 0x4004 0008) bit description . . . . .374
Table 340. Acceptance filter modes and access control .374
Table 341. Section configuration register settings. . . . . .375
Table 342. Acceptance Filter Mode Register (AFMR -
address 0x4003 C000) bit description . . . . . .378
Table 343. Standard Frame Individual Start Address register
(SFF_sa - address 0x4003 C004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .379
Table 344. Standard Frame Group Start Address register
(SFF_GRP_sa - address 0x4003 C008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .379
Table 345. Extended Frame Start Address register (EFF_sa
- address 0x4003 C00C) bit description . . . . .379
Table 346. Extended Frame Group Start Address register
(EFF_GRP_sa - address 0x4003 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .380
Table 347. End of AF Tables register (ENDofTable - address
0x4003 C014) bit description . . . . . . . . . . . . .380
Table 348. LUT Error Address register (LUTerrAd - address
0x4003 C018) bit description . . . . . . . . . . . . .381
Table 349. LUT Error register (LUTerr - address
0x4003 C01C) bit description . . . . . . . . . . . . .381
Table 350. Global FullCAN Enable register (FCANIE -
address 0x4003 C020) bit description . . . . . .381
Table 351. FullCAN Interrupt and Capture register 0
(FCANIC0 - address 0x4003 C024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .381
Table 352. FullCAN Interrupt and Capture register 1
(FCANIC1 - address 0x4003 C028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .382
Table 353. Format of automatically stored Rx messages385
Table 354. FullCAN semaphore operation. . . . . . . . . . . .385
Table 355. Example of Acceptance Filter Tables and ID index
Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
Table 356. Used ID-Look-up Table sections . . . . . . . . . .397
Table 357. Used ID-Look-up Table sections . . . . . . . . . .398
Table 358. SPI pin description. . . . . . . . . . . . . . . . . . . . .403
Table 359. SPI Data To Clock Phase Relationship . . . . .404
Table 360. SPI register map . . . . . . . . . . . . . . . . . . . . . .407
Table 361: SPI Control Register (S0SPCR - address
0x4002 0000) bit description . . . . . . . . . . . . .408
Table 362: SPI Status Register (S0SPSR - address
0x4002 0004) bit description . . . . . . . . . . . . . 409
Table 363: SPI Data Register (S0SPDR - address
0x4002 0008) bit description . . . . . . . . . . . . . 409
Table 364: SPI Clock Counter Register (S0SPCCR - address
0x4002 000C) bit description . . . . . . . . . . . . . 410
Table 365: SPI Test Control Register (SPTCR - address
0x4002 0010) bit description . . . . . . . . . . . . . 410
Table 366: SPI Test Status Register (SPTSR - address
0x4002 0014) bit description . . . . . . . . . . . . . 410
Table 367: SPI Interrupt Register (S0SPINT - address
0x4002 001C) bit description . . . . . . . . . . . . . 411
Table 368. SSP pin descriptions. . . . . . . . . . . . . . . . . . . 414
Table 369. SSP Register Map. . . . . . . . . . . . . . . . . . . . . 422
Table 370: SSPn Control Register 0 (SSP0CR0 - address
0x4008 8000, SSP1CR0 - 0x4003 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Table 371: SSPn Control Register 1 (SSP0CR1 - address
0x4008 8004, SSP1CR1 - 0x4003 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Table 372: SSPn Data Register (SSP0DR - address
0x4008 8008, SSP1DR - 0x4003 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Table 373: SSPn Status Register (SSP0SR - address
0x4008 800C, SSP1SR - 0x4003 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Table 374: SSPn Clock Prescale Register (SSP0CPSR -
address 0x4008 8010, SSP1CPSR -
0x4003 0010) bit description . . . . . . . . . . . . . 425
Table 375: SSPn Interrupt Mask Set/Clear register
(SSP0IMSC - address 0x4008 8014, SSP1IMSC -
0x4003 0014) bit description . . . . . . . . . . . . . 426
Table 376: SSPn Raw Interrupt Status register (SSP0RIS -
address 0x4008 8018, SSP1RIS - 0x4003 0018)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 426
Table 377: SSPn Masked Interrupt Status register (SSPnMIS
-address 0x4008 801C, SSP1MIS -
0x4003 001C) bit description . . . . . . . . . . . . . 427
Table 378: SSPn interrupt Clear Register (SSP0ICR -
address 0x4008 8020, SSP1ICR - 0x4003 0020)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 427
Table 379: SSPn DMA Control Register (SSP0DMACR -
address 0x4008 8024, SSP1DMACR -
0
x
4003 0024) bit description . . . . . . . . . . . . . 428
Table 380. I
2
C Pin Description . . . . . . . . . . . . . . . . . . . . 431
Table 381. I2C0CONSET, I2C1CONSET and I2C2CONSET
used to configure Master mode . . . . . . . . . . . 432
Table 382. I2C0CONSET, I2C1CONSET and I2C2CONSET
used to configure Slave mode . . . . . . . . . . . . 434
Table 383. I
2
C register map . . . . . . . . . . . . . . . . . . . . . . 440
Table 384. I
2
C Control Set register (I2CONSET: I
2
C0,
I2C0CONSET - address 0x4001 C000, I
2
C1,
I2C1CONSET - address 0x4005 C000, I
2
C2,
I2C2CONSET - address 0x400A 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Table 385. I
2
C Control Clear register (I2CONCLR: I
2
C0,
I2C0CONCLR - 0x4001 C018;
I
2
C1, I2C1CONCLR - 0x4005 C018; I
2
C2,
I2C2CONCLR - 0x400A 0018) bit
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