NXP Semiconductors LPC1768 - Page 809

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 809 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
0x4009 C01C) bit description . . . . . . . . . . . . .309
Table 282: UARTn Auto-baud Control Register (U0ACR -
address 0x4000 C020, U2ACR - 0x4009 8020,
U3ACR - 0x4009 C020) bit description . . . . .309
Table 283: UARTn IrDA Control Register (U0ICR - 0x4000
C024, U2ICR - 0x4009 8024, U3ICR - 0x4009
C024) bit description . . . . . . . . . . . . . . . . . . .312
Table 284: IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . .313
Table 285: UARTn Fractional Divider Register (U0FDR -
address 0x4000 C028, U2FDR - 0x4009 8028,
U3FDR - 0x4009 C028) bit description. . . . . .313
Table 286. Fractional Divider setting look-up table . . . . .316
Table 287: UARTn Transmit Enable Register (U0TER -
address 0x4000 C030, U2TER - 0x4009 8030,
U3TER - 0x4009 C030) bit description. . . . . .317
Table 288: UART1 Pin Description . . . . . . . . . . . . . . . . .320
Table 289: UART1 register map . . . . . . . . . . . . . . . . . . .321
Table 290: UART1 Receiver Buffer Register (U1RBR -
address 0x4001 0000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .322
Table 291: UART1 Transmitter Holding Register (U1THR -
address 0x4001 0000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .322
Table 292: UART1 Divisor Latch LSB Register (U1DLL -
address 0x4001 0000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .323
Table 293: UART1 Divisor Latch MSB Register (U1DLM -
address 0x4001 0004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .323
Table 294: UART1 Interrupt Enable Register (U1IER -
address 0x4001 0004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .323
Table 295: UART1 Interrupt Identification Register (U1IIR -
address 0x4001 0008) bit description. . . . . . .324
Table 296: UART1 Interrupt Handling . . . . . . . . . . . . . . .325
Table 297: UART1 FIFO Control Register (U1FCR - address
0x4001 0008) bit description . . . . . . . . . . . . .326
Table 298: UART1 Line Control Register (U1LCR - address
0x4001 000C) bit description . . . . . . . . . . . . .327
Table 299: UART1 Modem Control Register (U1MCR -
address 0x4001 0010) bit description. . . . . . .328
Table 300: Modem status interrupt generation . . . . . . . .329
Table 301: UART1 Line Status Register (U1LSR - address
0x4001 0014) bit description . . . . . . . . . . . . .330
Table 302: UART1 Modem Status Register (U1MSR -
address 0x4001 0018) bit description. . . . . . .331
Table 303: UART1 Scratch Pad Register (U1SCR - address
0x4001 0014) bit description . . . . . . . . . . . . .332
Table 304: Auto-baud Control Register (U1ACR - address
0x4001 0020) bit description . . . . . . . . . . . . .332
Table 305: UART1 Fractional Divider Register (U1FDR -
address 0x4001 0028) bit description. . . . . . .336
Table 306. Fractional Divider setting look-up table . . . . .338
Table 307: UART1 Transmit Enable Register (U1TER -
address 0x4001 0030) bit description. . . . . . .339
Table 308: UART1 RS485 Control register (U1RS485CTRL -
address 0x4001 004C) bit description . . . . . .339
Table 309. UART1 RS-485 Address Match register
(U1RS485ADRMATCH - address 0x4001 0050)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 340
Table 310. UART1 RS-485 Delay value register
(U1RS485DLY - address 0x4001 0054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Table 311. CAN Pin descriptions. . . . . . . . . . . . . . . . . . . 345
Table 312. Memory map of the CAN block . . . . . . . . . . . 350
Table 313. CAN acceptance filter and central CAN
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 314. CAN1 and CAN2 controller register map . . . 350
Table 315. CAN1 and CAN2 controller register summary352
Table 316. CAN Wake and Sleep registers. . . . . . . . . . . 352
Table 317. CAN Mode register (CAN1MOD - address
0x4004 4000, CAN2MOD - address
0x4004 8000) bit description . . . . . . . . . . . . . 353
Table 318. CAN Command Register (CAN1CMR - address
0x4004 4004, CAN2CMR - address 0x4004 8004)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 354
Table 319. CAN Global Status Register (CAN1GSR -
address 0x4004 4008, CAN2GSR - address
0x4004 8008) bit description . . . . . . . . . . . . . 356
Table 320. CAN Interrupt and Capture Register (CAN1ICR -
address 0x4004 400C, CAN2ICR - address
0x4004 800C) bit description . . . . . . . . . . . . 358
Table 321. CAN Interrupt Enable Register (CAN1IER -
address 0x4004 4010, CAN2IER - address
0x4004 8010) bit description . . . . . . . . . . . . . 361
Table 322. CAN Bus Timing Register (CAN1BTR - address
0x4004 4014, CAN2BTR - address 0x4004 8014)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 362
Table 323. CAN Error Warning Limit register (CAN1EWL -
address 0x4004 4018, CAN2EWL - address
0x4004 8018) bit description . . . . . . . . . . . . . 363
Table 324. CAN Status Register (CAN1SR - address
0x4004 401C, CAN2SR - address 0x4004 801C)
bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Table 325. CAN Receive Frame Status register (CAN1RFS -
address 0x4004 4020, CAN2RFS - address
0x4004 8020) bit description . . . . . . . . . . . . . 366
Table 326. CAN Receive Identifier register (CAN1RID -
address 0x4004 4024, CAN2RID - address
0x4004 8024) bit description . . . . . . . . . . . . . 366
Table 327. RX Identifier register when FF = 1 . . . . . . . . 367
Table 328. CAN Receive Data register A (CAN1RDA -
address 0x4004 4028, CAN2RDA - address
0x4004 8028) bit description . . . . . . . . . . . . . 367
Table 329. CAN Receive Data register B (CAN1RDB -
address 0x4004 402C, CAN2RDB - address
0x4004 802C) bit description . . . . . . . . . . . . . 367
Table 330. CAN Transmit Frame Information register
(CAN1TFI[1/2/3] - address 0x4004 40[30/40/50],
CAN2TFI[1/2/3] - 0x4004 80[30/40/50]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
T
a
ble 331. CAN Transfer Identifier register (CAN1TID[1/2/3]
- address 0x4004 40[34/44/54], CAN2TID[1/2/3] -
address 0x4004 80[34/44/54]) bit description 369
Table 332. Transfer Identifier register when FF = 1 . . . . 369