UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 808 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
Table 229. USB EP DMA Disable register (USBEpDMADis -
address 0x5000 C28C) bit description. . . . . .239
Table 230. USB DMA Interrupt Status register
(USBDMAIntSt - address 0x5000 C290) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Table 231. USB DMA Interrupt Enable register
(USBDMAIntEn - address 0x5000 C294) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Table 232. USB End of Transfer Interrupt Status register
(USBEoTIntSt - address 0x5000 C2A0s) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Table 233. USB End of Transfer Interrupt Clear register
(USBEoTIntClr - address 0x5000 C2A4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Table 234. USB End of Transfer Interrupt Set register
(USBEoTIntSet - address 0x5000 C2A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Table 235. USB New DD Request Interrupt Status register
(USBNDDRIntSt - address 0x5000 C2AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Table 236. USB New DD Request Interrupt Clear register
(USBNDDRIntClr - address 0x5000 C2B0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Table 237. USB New DD Request Interrupt Set register
(USBNDDRIntSet - address 0x5000 C2B4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .242
Table 238. USB System Error Interrupt Status register
(USBSysErrIntSt - address 0x5000 C2B8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .242
Table 239. USB System Error Interrupt Clear register
(USBSysErrIntClr - address 0x5000 C2BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .242
Table 240. USB System Error Interrupt Set register
(USBSysErrIntSet - address 0x5000 C2C0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .242
Table 241. SIE command code table. . . . . . . . . . . . . . . .246
Table 242. Set Address command bit description . . . . . .246
Table 243. Configure Device command bit description . .247
Table 244. Set Mode command bit description . . . . . . . .247
Table 245. Set Device Status command bit description. .248
Table 246. Get Error Code command bit description. . . .250
Table 247. Read Error Status command bit description .250
Table 248. Select Endpoint command bit description . . .251
Table 249. Set Endpoint Status command bit description252
Table 250. Clear Buffer command bit description . . . . . .253
Table 251. DMA descriptor . . . . . . . . . . . . . . . . . . . . . . .257
Table 252. USB (OHCI) related acronyms and abbreviations
used in this chapter . . . . . . . . . . . . . . . . . . . .270
Table 253. USB Host port pins . . . . . . . . . . . . . . . . . . . .272
Table 254. USB Host register address definitions . . . . .272
Table 255. USB OTG port pins . . . . . . . . . . . . . . . . . . . .276
Table 256. USB OTG and I2C register address
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
Table 257. USB Interrupt Status register - (USBIntSt -
address 0x5000 C1C0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .278
Table 258. OTG Interrupt Status register (OTGIntSt -
address 0x5000 C100) bit description . . . . . .279
Table 259. OTG Status Control register (OTGStCtrl - address
0x5000 C110) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 260. OTG Timer register (OTGTmr - address
0x5000 C114) bit description . . . . . . . . . . . . . 281
Table 261. OTG clock control register (OTG_clock_control -
address 0x5000 CFF4) bit description . . . . . 281
Table 262. OTG clock status register (OTGClkSt - address
0x5000 CFF8) bit description. . . . . . . . . . . . . 282
Table 263. I2C Receive register (I2C_RX - address
0x5000 C300) bit description . . . . . . . . . . . . . 283
Table 264. I2C Transmit register (I2C_TX - address
0x5000 C300) bit description . . . . . . . . . . . . . 283
Table 265. I2C status register (I2C_STS - address
0x5000 C304) bit description . . . . . . . . . . . . 283
Table 266. I2C Control register (I2C_CTL - address
0x5000 C308) bit description . . . . . . . . . . . . 285
Table 267. I2C_CLKHI register (I2C_CLKHI - address
0x5000 C30C) bit description. . . . . . . . . . . . . 286
Table 268. I2C_CLKLO register (I2C_CLKLO - address
0x5000 C310) bit description . . . . . . . . . . . . . 286
Table 269: UARTn Pin description . . . . . . . . . . . . . . . . . 300
Table 270. UART0/2/3 Register Map . . . . . . . . . . . . . . . 301
Table 271: UARTn Receiver Buffer Register (U0RBR -
address 0x4000 C000, U2RBR - 0x4009 8000,
U3RBR - 04009 C000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 272: UARTn Transmit Holding Register (U0THR -
address 0x4000 C000, U2THR - 0x4009 8000,
U3THR - 0x4009 C000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 273: UARTn Divisor Latch LSB register (U0DLL -
address 0x4000 C000, U2DLL - 0x4009 8000,
U3DLL - 0x4009 C000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 274: UARTn Divisor Latch MSB register (U0DLM -
address 0x4000 C004, U2DLM - 0x4009 8004,
U3DLM - 0x4009 C004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 275: UARTn Interrupt Enable Register (U0IER -
address 0x4000 C004, U2IER - 0x4009 8004,
U3IER - 0x4009 C004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 276: UARTn Interrupt Identification Register (U0IIR -
address 0x4000 C008, U2IIR - 0x4009 8008,
U3IIR - 0x4009 C008) bit description. . . . . . . 304
Table 277: UARTn Interrupt Handling. . . . . . . . . . . . . . . 305
Table 278: UARTn FIFO Control Register (U0FCR - address
0x4000 C008, U2FCR - 0x4009 8008, U3FCR -
0x4007 C008) bit description . . . . . . . . . . . . . 306
Table 279: UARTn Line Control Register (U0LCR - address
0x4000 C00C, U2LCR - 0x4009 800C, U3LCR -
0x4009 C00C) bit description. . . . . . . . . . . . . 307
Table 280: UARTn Line Status Register (U0LSR - address
0x4000 C014, U2LSR - 0x4009 8014, U3LSR -
0x4009 C014) bit description . . . . . . . . . . . . 308
Table 281: UARTn Scratch Pad Register (U0SCR - address
0x4000 C01C, U2SCR - 0x4009 801C, U3SCR -
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