NXP Semiconductors LPC1768 - Page 831

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 831 of 841
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NXP Semiconductors
UM10360
Chapter 35: Supplementary information
20.5 Register description . . . . . . . . . . . . . . . . . . . 477
20.5.1 Digital Audio Output register (I2SDAO -
0x400A 8000) . . . . . . . . . . . . . . . . . . . . . . . . 477
20.5.2 Digital Audio Input register (I2SDAI -
0x400A 8004) . . . . . . . . . . . . . . . . . . . . . . . . 478
20.5.3 Transmit FIFO register (I2STXFIFO -
0x400A 8008) . . . . . . . . . . . . . . . . . . . . . . . . 478
20.5.4 Receive FIFO register (I2SRXFIFO -
0x400A 800C). . . . . . . . . . . . . . . . . . . . . . . . 478
20.5.5 Status Feedback register (I2SSTATE -
0x400A 8010) . . . . . . . . . . . . . . . . . . . . . . . . 479
20.5.6 DMA Configuration Register 1 (I2SDMA1 -
0x400A 8014) . . . . . . . . . . . . . . . . . . . . . . . . 479
20.5.7 DMA Configuration Register 2 (I2SDMA2 -
0x400A 8018) . . . . . . . . . . . . . . . . . . . . . . . . 480
20.5.8 Interrupt Request Control register (I2SIRQ -
0x400A 801C). . . . . . . . . . . . . . . . . . . . . . . . 480
20.5.9 Transmit Clock Rate register (I2STXRATE -
0x400A 8020). . . . . . . . . . . . . . . . . . . . . . . . 480
20.5.9.1 Notes on fractional rate generators . . . . . . . 481
20.5.10 Receive Clock Rate register (I2SRXRATE -
0x400A 8024). . . . . . . . . . . . . . . . . . . . . . . . 481
20.5.11 Transmit Clock Bit Rate register (I2STXBITRATE
- 0x400A 8028) . . . . . . . . . . . . . . . . . . . . . . 482
20.5.12 Receive Clock Bit Rate register (I2SRXBITRATE -
0x400A 802C) . . . . . . . . . . . . . . . . . . . . . . . 482
20.5.13 Transmit Mode Control register (I2STXMODE -
0x400A 8030). . . . . . . . . . . . . . . . . . . . . . . . 482
20.5.14 Receive Mode Control register (I2SRXMODE -
0x400A 8034). . . . . . . . . . . . . . . . . . . . . . . . 483
20.6 I
2
S transmit and receive interfaces . . . . . . . 484
20.7 I
2
S operating modes . . . . . . . . . . . . . . . . . . . 485
20.8 FIFO controller . . . . . . . . . . . . . . . . . . . . . . . 489
Chapter 21: LPC176x/5x Timer 0/1/2/3
21.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 491
21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
21.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 492
21.4 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 492
21.5 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 492
21.5.1 Multiple CAP and MAT pins . . . . . . . . . . . . . 492
21.6 Register description . . . . . . . . . . . . . . . . . . . 493
21.6.1 Interrupt Register (T[0/1/2/3]IR - 0x4000 4000,
0x4000 8000, 0x4009 0000, 0x4009 4000) . 494
21.6.2 Timer Control Register (T[0/1/2/3]CR -
0x4000 4004, 0x4000 8004, 0x4009 0004,
0x4009 4004) . . . . . . . . . . . . . . . . . . . . . . . . 494
21.6.3 Count Control Register (T[0/1/2/3]CTCR -
0x4000 4070, 0x4000 8070, 0x4009 0070,
0x4009 4070) . . . . . . . . . . . . . . . . . . . . . . . . 495
21.6.4 Timer Counter . . . . . . . .registers (T0TC - T3TC,
0x4000 4008, 0x4000 8008, 0x4009 0008,
0x4009 4008) . . . . . . . . . . . . . . . . . . . . . . . . 496
21.6.5 Prescale register (T0PR - T3PR, 0x4000 400C,
0x4000 800C, 0x4009 000C, 0x4009 400C) 496
21.6.6 Prescale Counter register (T0PC - T3PC,
0x4000 4010, 0x4000 8010, 0x4009 0010,
0x4009 4010) . . . . . . . . . . . . . . . . . . . . . . . . 496
21.6.7 Match Registers (MR0 - MR3) . . . . . . . . . . . 497
21.6.8 Match Control Register (T[0/1/2/3]MCR -
0x4000 4014, 0x4000 8014, 0x4009 0014,
0x4009 4014) . . . . . . . . . . . . . . . . . . . . . . . . 497
21.6.9 Capture Registers (CR0 - CR1). . . . . . . . . . 498
21.6.10 Capture Control Register (T[0/1/2/3]CCR -
0x4000 4028, 0x4000 8028, 0x4009 0028,
0x4009 4028) . . . . . . . . . . . . . . . . . . . . . . . . 498
21.6.11 External Match Register (T[0/1/2/3]EMR -
0x4000 403C, 0x4000 803C, 0x4009 003C,
0x4009 403C) . . . . . . . . . . . . . . . . . . . . . . . 498
21.6.12 DMA operation. . . . . . . . . . . . . . . . . . . . . . . 499
21.7 Example timer operation . . . . . . . . . . . . . . . 500
21.8 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 501
Chapter 22: LPC176x/5x Repetitive Interrupt Timer (RIT)
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
22.2 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 502
22.3 Register description . . . . . . . . . . . . . . . . . . . 502
22.3.1 RI Compare Value register (RICOMPVAL -
0x400B 0000) . . . . . . . . . . . . . . . . . . . . . . . . 502
22.3.2 RI Mask register (RIMASK - 0x400B 0004) . 502
22.3.3 RI Control register (RICTRL - 0x400B 0008) 503
22.3.4 RI Counter register (RICOUNTER - 0x400B
000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
22.4 RI timer operation . . . . . . . . . . . . . . . . . . . . . 503
Chapter 23: LPC176x/5x System Tick Timer
23.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 505 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505