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ST STM32G0 1 Series User Manual

ST STM32G0 1 Series
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Universal serial bus full-speed host/device interface (USB) RM0444
1288/1390 RM0444 Rev 5
Bit 13 ERR: Error
This flag is set whenever one of the errors listed below has occurred:
NANS: No ANSwer. The timeout for a host response has expired.
CRC: Cyclic redundancy check error. One of the received CRCs, either in the token or in
the data, was wrong.
BST: Bit stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or
CRC.
FVIO: Framing format violation. A non-standard frame was received (EOP not in the right
place, wrong token sequence, etc.).
The USB software can usually ignore errors, since the USB peripheral and the PC host
manage retransmission in case of errors in a fully transparent way. This interrupt can be
useful during the software development phase, or to monitor the quality of transmission over
the USB bus, to flag possible problems to the user (for example loose connector, too noisy
environment, broken conductor in the USB cable and so on). This bit is read/write but only 0
can be written and writing 1 has no effect.
Bit 12 WKUP: Wakeup
This bit is set to 1 by the hardware when, during suspend mode, activity is detected that
wakes up the USB peripheral. This event asynchronously clears the SUSPRDY bit in the
CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of
the device (for example wakeup unit) about the start of the resume process. This bit is
read/write but only 0 can be written and writing 1 has no effect.
Bit 11 SUSP: Suspend mode request
Device mode
This bit is set by the hardware when no traffic has been received for 3 ms, indicating a
suspend mode request from the USB bus. The suspend condition check is enabled
immediately after any USB reset and it is disabled by the hardware when the suspend mode
is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only 0 can
be written and writing 1 has no effect.
Bit 10 RST_DCON: USB reset request (Device mode) or device connect/disconnect (Host mode)
Device mode
This bit is set by hardware when an USB reset is released by the host and the bus returns to
idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles.
Host mode
This bit is set by hardware when device connection or device disconnection is detected.
Device connection is signaled after J state is sampled for 22 cycles consecutively from
unconnected state. Device disconnection is signaled after SE0 state is seen for 22 bit times
consecutively from connected state.
Bit 9 SOF: Start of frame
This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives
through the USB bus. The interrupt service routine may monitor the SOF events to have a
1 ms synchronization event to the USB host and to safely read the USB_FNR register which
is updated at the SOF packet reception (this could be useful for isochronous applications).
This bit is read/write but only 0 can be written and writing 1 has no effect.
Bit 8 ESOF: Expected start of frame
Device mode
This bit is set by the hardware when an SOF packet is expected but not received. The host
sends an SOF packet each 1 ms, but if the device does not receive it properly, the
suspend
timer issues this interrupt. If three consecutive ESOF interrupts are generated (for example
three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is
generated. This bit is set even when the missing SOF packets occur while the
suspend timer
is not yet locked. This bit is read/write but only 0 can be written and writing 1 has no effect.

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ST STM32G0 1 Series Specifications

General IconGeneral
BrandST
ModelSTM32G0 1 Series
CategoryMicrocontrollers
LanguageEnglish

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