ST STM32G0 1 Series - Page 211

RM0444 Rev 5 211/1390
RM0444 Reset and clock control (RCC)
220
Bits 19:18 LPTIM1SEL[1:0]: LPTIM1 clock source selection
This bitfield is controlled by software to select LPTIM1 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
Bits 17:16 Reserved, must be kept at reset value.
Bits 15:14 I2C2I2S1SEL[1:0]: I2C2/I2S1 clock source selection
This bitfield is controlled by software to select I2S1/I2C2 clock source as follows:
00: PCLK/SYSCLK
01: SYSCLK/PLLPCLK
10: HSI16/HSI16
11: Reserved/I2S_CKIN
Note: On the STM32G0B1xx and STM32G0C1xx, the bitfield selects the clock to the I2C2
peripheral. On the other devices, it selects the clock to the I2S1 peripheral.
Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection
This bitfield is controlled by software to select I2C1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: Reserved
Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection
This bitfield is controlled by software to select LPUART1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 9:8 LPUART2SEL[1:0]: LPUART2 clock source selection
(1)
This bitfield is controlled by software to select LPUART2 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bit 7 Reserved, must be kept at reset value.
Bit 6 CECSEL: HDMI CEC clock source selection
This bit is set and cleared by software. It selects the HDMI CEC clock source as follows:
0: HSI16 divided by 488
1: LSE