DocID024597 Rev 3 1347/1693
RM0351 Serial audio interface (SAI)
1362
Bits 31:24 Reserved, always read as 0.
Bits 23:20 MCKDIV[3:0]: Master clock divider.
These bits are set and cleared by software. These bits are meaningless when the audio block
operates in slave mode. They have to be configured when the audio block is disabled.
0000: Divides by 1 the master clock input.
Others: the master clock frequency is calculated accordingly to the following formula:
Bit 19 NODIV: No divider.
This bit is set and cleared by software.
0: Master clock generator is enabled
1: No divider used in the clock generator (in this case Master Clock Divider bit has no effect)
Bit 18 Reserved, always read as 0.
Bit 17 DMAEN: DMA enable.
This bit is set and cleared by software.
0: DMA disabled
1: DMA enabled
Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must
be configured before setting DMAEN to avoid a DMA request in receiver mode.
Bit 16 SAIXEN: Audio block enable where x is A or B.
This bit is set by software.
To switch off the audio block, the application software must program this bit to 0 and poll the bit till it
reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it
is set to 0, otherwise the enable command will not be taken into account.
This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer
is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame
transfer.
0: SAIx audio block disabled
1: SAIx audio block enabled.
Note: When SAIx block is configured in master mode, the kernel clock must be present on the input of
SAIx before setting SAIXEN bit.
Bits 15:14 Reserved, always read as 0.
Bit 13 OUTDRIV: Output drive.
This bit is set and cleared by software.
0: Audio block output driven when SAIXEN is set
1: Audio block output driven immediately after the setting of this bit.
Note: This bit has to be set before enabling the audio block and after the audio block configuration.
Bit 12 MONO: Mono mode.
This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2.
When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates
as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are
stored. Refer to Section : Mono/stereo mode for more details.
0: Stereo mode
1: Mono mode.
F
SCK_x
F
SAI_CK_x
MCKDIV 2×
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