DocID024597 Rev 3 155/1693
RM0351 Power control (PWR)
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I/O states in Stop 2 mode
In the Stop 2 mode, all I/O pins keep the same state as in the Run mode.
Entering Stop 2 mode
The Stop 2 mode is entered according Section : Entering low power mode, when the
SLEEPDEEP bit in the Cortex
®
-M4 System Control register is set.
Refer to Table 26: Stop 2 mode for details on how to enter the Stop 2 mode.
Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode
from the Low-power run mode.
If Flash memory programming is ongoing, the Stop 2 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB
access is finished.
In Stop 2 mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 32.3: IWDG functional description in Section 32: Independent watchdog
(IWDG).
• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
• Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR).
Several peripherals can be used in Stop 2 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1,
I2C3, LPUART.
The comparators can be used in Stop 2 mode, the PVMx (x=1,2,3,4) and the PVD as well. If
they are not needed, they must be disabled by software to save their power consumptions.
The ADCx, OPAMPx, DACx, temperature sensor and VREFBUF buffer can consume power
during Stop 2 mode, unless they are disabled before entering this mode.
All the peripherals which cannot be enabled in Stop 2 mode must be either disabled by
clearing the Enable bit in the peripheral itself, or put under reset state by setting the
corresponding bit in the AHB1 peripheral reset register (RCC_AHB1RSTR), AHB2
peripheral reset register (RCC_AHB2RSTR), AHB3 peripheral reset register
(RCC_AHB3RSTR), APB1 peripheral reset register 1 (RCC_APB1RSTR1), APB1
peripheral reset register 2 (RCC_APB1RSTR2), APB2 peripheral reset register
(RCC_APB2RSTR).
Exiting Stop 2 mode
The Stop 2 mode is exit according Section : Exiting low power mode.
Refer to Table 26: Stop 2 mode for details on how to exit Stop 2 mode.
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