DocID024597 Rev 3 167/1693
RM0351 Power control (PWR)
178
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 PVMO4: Peripheral voltage monitoring output: V
DDA
vs. 2.2 V
0: V
DDA
voltage is above PVM4 threshold (around 2.2 V).
1: V
DDA
voltage is below PVM4 threshold (around 2.2 V).
Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the
PVM4 output is valid after the PVM4 wakeup time.
Bit 14 PVMO3: Peripheral voltage monitoring output: V
DDA
vs. 1.62 V
0: V
DDA
voltage is above PVM3 threshold (around 1.62 V).
1: V
DDA
voltage is below PVM3 threshold (around 1.62 V).
Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the
PVM3 output is valid after the PVM3 wakeup time.
Bit 13 PVMO2: Peripheral voltage monitoring output: V
DDIO2
vs. 0.9 V
0: V
DDIO2
voltage is above PVM2 threshold (around 0.9 V).
1: V
DDIO2
voltage is below PVM2 threshold (around 0.9 V).
Note: PVMO2 is cleared when PVM2 is disabled (PVME2 = 0). After enabling PVM2, the
PVM2 output is valid after the PVM2 wakeup time.
Bit 12 PVMO1: Peripheral voltage monitoring output: V
DDUSB
vs. 1.2 V
0: V
DDUSB
voltage is above PVM1 threshold (around 1.2 V).
1: V
DDUSB
voltage is below PVM1 threshold (around 1.2 V).
Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the
PVM1 output is valid after the PVM1 wakeup time.
Bit 11 PVDO: Power voltage detector output
0: V
DD
is above the selected PVD threshold
1: V
DD
is below the selected PVD threshold
Bit 10 VOSF: Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR_CR1 register.
0: The regulator is ready in the selected voltage range
1: The regulator output voltage is changing to the required voltage level
Bit 9 REGLPF: Low-power regulator flag
This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits
from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode.
A polling on this bit must be done before increasing the product frequency.
This bit is cleared by hardware when the regulator is ready.
0: The regulator is ready in main mode (MR)
1: The regulator is in low-power mode (LPR)
Bit 8 REGLPS: Low-power regulator started
This bit provides the information whether the low-power regulator is ready after a power-on
reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still
cleared, the wakeup from Standby mode time may be increased.
0: The low-power regulator is not ready
1: The low-power regulator is ready
Bits 7:0 Reserved, must be kept at reset value.
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