DocID024597 Rev 3 513/1693
RM0351 Analog-to-digital converters (ADC)
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Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
0000: Event 0
0001: Event 1
0010: Event 2
0011: Event 3
0100: Event 4
0101: Event 5
0110: Event 6
0111: Event 7
...
1111: Event 15
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Section : Data
register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN)
0: Right alignment
1: Left alignment
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit
01: 10-bit
10: 8-bit
11: 6-bit
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot Mode selected
1: DMA Circular Mode selected
For more details, refer to Section : Managing conversions using the DMA
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the
ADCx_CCR register.
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows to use
the GP-DMA to manage automatically the converted data. For more details, refer to Section :
Managing conversions using the DMA.
0: DMA disabled
1: DMA enabled
Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures
that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the
ADCx_CCR register.
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