Digital filter for sigma delta modulators (DFSDM) RM0351
612/1693 DocID024597 Rev 3
If Manchester data format is used, then the clock absence means that the clock recovery is
unable to perform from Manchester coded signal. For a correct clock recovery, it is first
necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 150 for Manchester
synchronization).
The detection of a clock absence in Manchester coding (after a first successful
synchronization) is based on changes comparison of coded serial data input signal with
output clock generation (DFSDM_CKOUT signal). There must be a voltage level change on
DFSDM_DATINy pin during 2 periods of DFSDM_CKOUT signal (which is controlled by
CKOUTDIV bits in DFSDM_CHCFG0R1 register). This condition also defines the minimum
data rate to be able to correctly recover the Manchester coded data and clock signals.
The maximum data rate of Manchester coded data must be less than the DFSDM_CKOUT
signal.
So to correctly receive Manchester coded data, the CKOUTDIV divider must be set
according the formula:
A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in
case of an input clock recovery error (see CKABF[7:0] in DFSDMx_ISR register and
CKABEN in DFSDMx_CHCFGyR1). After a clock absence flag clearing (by CLRCKABF in
DFSDMx_ICR register), the clock absence flag is refreshed.
CKOUTDIV 1+()T
SYSCLK
×()T
Manchester clock
2 CKOUTDIV× T
SYSCLK
×()<<
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