DocID024597 Rev 3 683/1693
RM0351 Liquid crystal display controller (LCD)
690
Bits 31:26 Reserved, must be kept at reset value
Bits 25:22 PS[3:0]: PS 16-bit prescaler
These bits are written by software to define the division factor of the PS 16-bit prescaler.
ck_ps = LCDCLK/(2). See
Section 22.3.2.
0000: ck_ps = LCDCLK
0001: ck_ps = LCDCLK/2
0002: ck_ps = LCDCLK/4
...
1111:ck_ps = LCDCLK/32768
Bits 21:18 DIV[3:0]: DIV clock divider
These bits are written by software to define the division factor of the DIV divider. See
Section 22.3.2.
0000: ck_div = ck_ps/16
0001: ck_div = ck_ps/17
0002: ck_div = ck_ps/18
...
1111:ck_div = ck_ps/31
Bits 17:16 BLINK[1:0]: Blink mode selection
00: Blink disabled
01: Blink enabled on SEG[0], COM[0] (1 pixel)
10: Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty)
11: Blink enabled on all SEGs and all COMs (all pixels)
Bits 15:13 BLINKF[2:0]: Blink frequency selection
000: f
LCD
/8
001: f
LCD
/16
010: f
LCD
/32
011: f
LCD
/64
100: f
LCD
/128
101: f
LCD
/256
110: f
LCD
/512
111: f
LCD
/1024
Bits 12:10 CC[2:0]: Contrast control
These bits specify one of the V
LCD
maximum voltages (independent of V
DD
). It ranges from
2.60 V to 3.51V.
000: V
LCD0
001: V
LCD1
010: V
LCD2
011: V
LCD3
100: V
LCD4
101: V
LCD5
110: V
LCD6
111: V
LCD7
Refer to the product datasheet for the V
LCDx
values.