ST STM32L4x6 User Manual

DocID024597 Rev 3 51/1693
RM0351 List of figures
60
Figure 49. NAND Flash controller waveforms for common memory access . . . . . . . . . . . . . . . . . . . 389
Figure 50. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Figure 51. QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Figure 52. An example of a read command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 53. An example of a DDR command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 54. nCS when CKMODE = 0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Figure 55. nCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 56. nCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 57. nCS when CKMODE = 1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 58. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Figure 59. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Figure 60. ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Figure 61. ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 62. ADC3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Figure 63. ADC calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Figure 64. Updating the ADC calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 65. Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 66. Enabling / Disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Figure 67. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 68. Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 69. Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 70. Triggers are shared between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 71. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Figure 72. Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 73. Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 74. Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 456
Figure 75. Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 456
Figure 76. Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 457
Figure 77. Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 457
Figure 78. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 458
Figure 79. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Figure 80. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 459
Figure 81. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 459
Figure 82. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 460
Figure 83. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 460
Figure 84. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Figure 85. Continuous conversion of a sequence, software trigger. . . . . . . . . . . . . . . . . . . . . . . . . . 462
Figure 86. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 87. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 88. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Figure 89. Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Figure 90. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Figure 91. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Figure 92. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Figure 93. AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 470
Figure 94. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Figure 95. AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . .

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English