List of figures RM0351
52/1693 DocID024597 Rev 3
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Figure 96. AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 473
Figure 97. AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Figure 98. Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Figure 99. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 476
Figure 100. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . . . . . . . . . . . 477
Figure 101. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 477
Figure 102. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 477
Figure 103. 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Figure 104. Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Figure 105. Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Figure 106. Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Figure 107. Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 482
Figure 108. Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Figure 109. Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Figure 110. Dual ADC block diagram
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Figure 111. Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 486
Figure 112. Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 488
Figure 113. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 490
Figure 114. Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . . . . . . . 490
Figure 115. Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Figure 116. Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Figure 117. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 493
Figure 118. Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Figure 119. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Figure 120. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 495
Figure 121. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Figure 122. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Figure 123. DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . . . . . . . . . . . . . . 496
Figure 124. DMA requests in regular simultaneous mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . 497
Figure 125. DMA requests in interleaved mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Figure 126. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Figure 127. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Figure 128. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Figure 129. DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Figure 130. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 131. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 132. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 545
Figure 133. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 134. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 547
Figure 135. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Figure 136. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 548
Figure 137. DAC sample and hold mode phases diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Figure 138. Comparators block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Figure 139. Window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Figure 140. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 141. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Figure 142. Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Figure 143. Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Figure 144. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . . 593
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