List of figures RM0351
54/1693 DocID024597 Rev 3
Figure 196. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 759
Figure 197. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Figure 198. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Figure 199. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Figure 200. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Figure 201. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 763
Figure 202. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 764
Figure 203. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
Figure 204. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 765
Figure 205. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
Figure 206. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 766
Figure 207. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 767
Figure 208. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 768
Figure 209. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Figure 210. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Figure 211. TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Figure 212. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 771
Figure 213. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
Figure 214. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Figure 215. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Figure 216. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Figure 217. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 775
Figure 218. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Figure 219. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 776
Figure 220. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Figure 221. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 777
Figure 222. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
Figure 223. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 224. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Figure 225. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
Figure 226. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 785
Figure 227. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Figure 228. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 787
Figure 229. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Figure 230. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 788
Figure 231. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 789
Figure 232. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Figure 233. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 793
Figure 234. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 794
Figure 235. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Figure 236. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Figure 237. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Figure 238. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 239. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
Figure 240. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Figure 241. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 801
Figure 242. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 802
Figure 243. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Figure 244. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 805
Figure 245. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Figure 246. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Figure 247. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
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