UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 817 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
Fig 88. Format of Slave Receiver mode . . . . . . . . . . . .434
Fig 89. Format of Slave Transmitter mode . . . . . . . . . .435
Fig 90. I
2
C serial interface block diagram . . . . . . . . . . .436
Fig 91. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .438
Fig 92. Serial clock synchronization. . . . . . . . . . . . . . . .438
Fig 93. Format and states in the Master Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .452
Fig 94. Format and states in the Master Receiver
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454
Fig 95. Format and states in the Slave Receiver mode.456
Fig 96. Format and states in the Slave Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
Fig 97. Simultaneous repeated START conditions from two
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465
Fig 98. Forced access to a busy I
2
C-bus. . . . . . . . . . . .465
Fig 99. Recovering from a bus obstruction caused by a
LOW level on SDA. . . . . . . . . . . . . . . . . . . . . . .465
Fig 100. Simple I2S configurations and bus timing . . . . .476
Fig 101. Typical transmitter master mode, with or without
MCLK output . . . . . . . . . . . . . . . . . . . . . . . . . . .486
Fig 102. Transmitter master mode sharing the receiver
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .486
Fig 103. 4-wire transmitter master mode sharing the receiver
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .486
Fig 104. Typical transmitter slave mode . . . . . . . . . . . . .486
Fig 105. Transmitter slave mode sharing the receiver
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .486
Fig 106. 4-wire transmitter slave mode sharing the receiver
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .487
Fig 107. Typical receiver master mode, with or without MCLK
output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .488
Fig 108. Receiver master mode sharing the transmitter
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .488
Fig 109. 4-wire receiver master mode sharing the transmitter
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .488
Fig 110. Typical receiver slave mode . . . . . . . . . . . . . . .488
Fig 111. Receiver slave mode sharing the transmitter
reference clock . . . . . . . . . . . . . . . . . . . . . . . . .488
Fig 112. 4-wire receiver slave mode sharing the transmitter
bit clock and WS . . . . . . . . . . . . . . . . . . . . . . . .489
Fig 113. FIFO contents for various I
2
S modes. . . . . . . . .490
Fig 114. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled.. . . . .500
Fig 115. A timer Cycle in Which PR=2, MRx=6, and both
interrupt and stop on match are enabled. . . . . .500
Fig 116. Timer block diagram . . . . . . . . . . . . . . . . . . . . .501
Fig 117. RI timer block diagram. . . . . . . . . . . . . . . . . . . .504
Fig 118. System Tick Timer block diagram . . . . . . . . . . .506
Fig 119. PWM block diagram. . . . . . . . . . . . . . . . . . . . . .512
Fig 120. Sample PWM waveforms . . . . . . . . . . . . . . . . .513
Fig 121. MCPWM Block Diagram . . . . . . . . . . . . . . . . . .524
Fig 122. Edge-aligned PWM waveform without dead time,
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
Fig 123. Center-aligned PWM waveform without dead time,
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539
Fig 124. Edge-aligned PWM waveform with dead time,
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539
Fig 125. Center-aligned waveform with dead time,
POLA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Fig 126. Three-phase DC mode sample waveforms . . . 542
Fig 127. Three-phase AC mode sample waveforms, edge
aligned PWM mode. . . . . . . . . . . . . . . . . . . . . . 543
Fig 128. Encoder interface block diagram . . . . . . . . . . . 545
Fig 129. Quadrature Encoder Basic Operation. . . . . . . . 547
Fig 130. RTC domain conceptual diagram . . . . . . . . . . . 560
Fig 131. RTC functional block diagram. . . . . . . . . . . . . . 560
Fig 132. Watchdog block diagram . . . . . . . . . . . . . . . . . 574
Fig 133. DAC control with DMA interrupt and timer . . . . 586
Fig 134. DMA controller block diagram. . . . . . . . . . . . . . 588
Fig 135. LLI example . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Fig 136. Map of lower memory . . . . . . . . . . . . . . . . . . . . 617
Fig 137. Boot process flowchart . . . . . . . . . . . . . . . . . . . 620
Fig 138. IAP parameter passing . . . . . . . . . . . . . . . . . . . 634
Fig 139. Algorithm for generating a 128 bit signature. . . 642
Fig 140. Typical Cortex-M3 implementation . . . . . . . . . . 646
Fig 141. ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Fig 142. LSR#3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Fig 143. LSL#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Fig 144. ROR#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Fig 145. RRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Fig 146. Bit-band mapping . . . . . . . . . . . . . . . . . . . . . . . 742
Fig 147. Little-endian format. . . . . . . . . . . . . . . . . . . . . . 743
Fig 148. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Fig 149. CFSR bit assignments . . . . . . . . . . . . . . . . . . . 778
Fig 150. SRD example . . . . . . . . . . . . . . . . . . . . . . . . . . 797
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