Main TLB
A unified main TLB handles misses from the micro TLBs.
In implementations with CPU cache protection, parity bits protect the TLB RAMs by
enabling the detection of any single-bit error. If an error is detected, the entry is flushed
and fetched again.
L1 data-side memory system
The L1 data-side memory system includes the Data Cache Unit (DCU), the Store Buffer (STB), and the
Bus Interface Unit.
DCU
The DCU manages all load and store operations.
In implementations with CPU cache protection, parity bits protect the L1 Data cache
tag RAMs and dirty RAMs. The L1 Data cache data RAMs are protected using Error
Correction Codes (ECC). The ECC scheme is Single Error Correct Double Error Detect
(SECDED). The DCU includes a combined local and global exclusive monitor that is
used by the Load-Exclusive/Store-Exclusive instructions.
STB
The STB holds store operations when they have left the load/store pipeline in the DCU
and have been committed by the DPU. The STB can request access to the cache RAMs
in the DCU, request the BIU to initiate linefills, or request the Bus Interface Unit (BIU)
to write out the data on the external write channel. External data writes are through the
SCU.
The STB is also used to queue maintenance operations before they are broadcast to
other cores in the processor.
BIU
The BIU contains the SCU interface and buffers to decouple the interface from the L1
Data cache and STB. The BIU and the SCU always operate at the processor frequency.
Governor
The governor block, outside the core, includes all functions that must remain operating while a core is in
retention mode.
GIC CPU interface
The GIC CPU interface is a memory-mapped interface through which a core receives
an interrupt. The GIC Distributor can read and write the GIC CPU interface registers
even while the core is in retention mode.
Generic timer
The Generic Timer has an interface to an external system counter. It provides a
consistent view of time, which can be used to schedule events and trigger interrupts. It
is also used by the retention circuits in the processor.
L2 Memory System
The L2 memory system contains the L2 cache pipeline and all the logic that maintains memory
coherence between the cores in the cluster.
SCU
The SCU connects the cores to the external memory system through the master
memory interface. It also maintains data cache coherency between the cores and
arbitrates L2 requests from the cores.
A2 Technical Overview
A2.1 Components
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A2-42
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