mini-SCU
The mini-SCU replaces the SCU in certain uniprocessor configurations that do not
require data cache coherency with other masters in the system. That is, implementations
that are configured to have a single core, no L2 cache, no CPU cache protection, and an
AXI interface. The mini-SCU bridges between the master interface of the core and the
AXI master interface of the processor.
L2 cache
Each Cortex‑A35 cluster can include an optional L2 cache that participates in the
coherency protocol. Each L2 cache is 8-way set associative, supports 64-byte cache
lines, and has a configurable cache RAM size between 128KB and 1MB.
ACP
The ACP interface cannot be configured without an L2 cache because it reuses
buffering and data paths implemented for the L2 cache to achieve optimal efficiency.
The main advantage of the ACP interface is its ability to allocate data in the L2 cache
RAMs.
Debug and trace components
Cross-trigger
The Cross Trigger Matrix (CTM) combines the CoreSight Cross Trigger Interface
(CTI) channel signals from all the cores so that a single cross trigger channel interface
is presented in the Cortex‑A35 processor. This module can combine up to four internal
channel interfaces corresponding to each core along with one external channel
interface.
Debug ROM
The Cortex‑A35 processor has a debug ROM which is a CoreSight feature.
ETM
The ETM trace unit is a build-time configuration option. This module performs real-
time instruction flow tracing that complies with the ETM architecture.
Related information
A2.2 Interfaces on page A2-44
A6.1 About the L1 memory system on page A6-90
A7.1 About the L2 memory system on page A7-98
Chapter A3 Clocks, Resets, and Input Synchronization on page A3-49
Chapter A4 Power Management on page A4-57
A2 Technical Overview
A2.1 Components
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A2-43
Non-Confidential
To Next Page
Loading...
Need help?
General
