ARM Cortex-A35 User Manual

0 Non-secure EL1 writes are not trapped. This is the reset value.
1 Non-secure EL1 writes are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TTLB, [25]
Traps TLB maintenance instructions. The possible values are:
0 Non-secure EL1 TLB maintenance instructions are not trapped. This is the reset value.
1 TLB maintenance instructions executed from Non-secure EL1that are not UNDEFINED are
trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TPU, [24]
Traps cache maintenance instructions to Point of Unification (POU). The possible values are:
0 Cache maintenance instructions are not trapped. This is the reset value.
1 Cache maintenance instructions to the POU executed from Non-secure EL1 or EL0 that are
not UNDEFINED are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TPC, [23]
Traps data or unified cache maintenance instructions to Point of Coherency (POC). The possible
values are:
0 Data or unified cache maintenance instructions are not trapped. This is the reset value.
1 Data or unified cache maintenance instructions by address to the POC executed from Non-
secure EL1 or EL0 that are not UNDEFINED are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TSW, [22]
Traps data or unified cache maintenance instructions by Set or Way. The possible values are:
0 Data or unified cache maintenance instructions are not trapped. This is the reset value.
1 Data or unified cache maintenance instructions by Set or Way executed from Non-secure
EL1 that are not UNDEFINED are trapped to EL2.are not trapped.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TACR, [21]
Traps Auxiliary Control registers. The possible values are:
0 Accesses to Auxiliary Control registers are not trapped. This is the reset value.
1 Accesses to ACTLR in AArch32 state or the ACTLR_EL1 in the AArch64 state from Non-
secure EL1 are trapped to EL2.
TIDCP, [20]
Trap Implementation Dependent functionality. When 1, this causes accesses to the following
instruction set space executed from Non-secure EL1 to be trapped to EL2:
B2 AArch64 system registers
B2.48 Hypervisor Configuration Register, EL2
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English