ARM Cortex-A35 User Manual

AArch32 All CP15 MCR and MRC instructions as follows:
• CRn is 9, Opcode1 is 0 to 7, CRm is c0, c1, c2, c5, c6, c7, or c8, and Opcode2 is
0 to 7.
• CRn is 10, Opcode1 is 0 to 7, CRm is c0, c1, c4, or c8, and Opcode2 is 0 to 7.
• CRn is 11, Opcode1 is 0 to 7, CRm is c0 to c8, or c15, and Opcode2 is 0 to 7.
AArch64 Reserved control space for IMPLEMENTATION DEFINED functionality.
Accesses from EL0 are UNDEFINED. The reset value is 0.
TSC, [19]
Traps SMC instruction. The possible values are:
0 SMC instruction in not trapped. This is the reset value.
1 SMC instruction executed in Non-secure EL1 is trapped to EL2 for AArch32 and AArch64
Execution states.
TID3, [18]
Traps ID group 3 registers. The possible values are:
0 ID group 3 register accesses are not trapped. This is the reset value.
1 Reads to ID group 3 registers executed from Non-secure EL1 are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TID2, [17]
Traps ID group 2 registers. The possible values are:
0 ID group 2 register accesses are not trapped. This is the reset value.
1 Reads to ID group 2 registers and writes to CSSELR and CSSELR_EL1executed from Non-
secure EL1 or EL0, if not UNDEFINED, are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TID1, [16]
Traps ID group 1 registers. The possible values are:
0 ID group 1 register accesses are not trapped. This is the reset value.
1 Reads to ID group 1registers executed from Non-secure EL1 are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TID0, [15]
Traps ID group 0 registers. The possible values are:
0 ID group 0 register accesses are not trapped. This is the reset value.
1 Reads to ID group 0 registers executed from Non-secure EL1 are trapped to EL2.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
registers covered by this setting.
TWE, [14]
Traps WFE instruction if it would cause suspension of execution. For example, if there is no
pending WFE event. The possible values are:
0 WFE instruction is not trapped. This is the reset value.
B2 AArch64 system registers
B2.48 Hypervisor Configuration Register, EL2
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English