1 WFE instruction executed in Non-secure EL1 or EL0 is trapped to EL2 for AArch32 and
AArch64 Execution states.
TWI, [13]
Traps WFI instruction if it causes suspension of execution. For example, if there is no pending
WFI event. The possible values are:
0 WFI instruction is not trapped. This is the reset value.
1 WFI instruction executed in Non-secure EL1 or EL0 is trapped to EL2 for AArch32 and
AArch64 Execution states.
DC, [12]
Default cacheable. When this bit is set it causes:
• SCTLR_EL1.M to behave as 0 for all purposes other than reading the bit.
• HCR_EL2.VM to behave as 1 for all purposes other than reading the bit.
The memory type produced by the first stage of translation in Non-secure EL1 and EL0 is Non-
Shareable, Inner Write-Back Write-Allocate, Outer Write-Back Write-Allocate. The reset value
is 0.
BSU, [11:10]
Barrier shareability upgrade. Determines the minimum shareability domain that is supplied to
any barrier executed from Non-secure EL1 or EL0. The possible values are:
0b00 No effect. This is the reset value.
0b01 Inner Shareable.
0b10 Outer Shareable.
0b11 Full system.
This value is combined with the specified level of the barrier held in its instruction, according to
the algorithm for combining shareability attributes.
FB, [9]
Forces broadcast. The possible values are:
0 Instructions are not broadcast. This is the reset value.
1 Forces instruction broadcast within Inner Shareable domain when executing from Non-
secure EL1.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for the
instructions covered by this setting.
VSE, [8]
Virtual System Error/Asynchronous Abort. The possible values are:
0 Virtual System Error/Asynchronous Abort is not pending by this mechanism. This is the reset
value.
1 Virtual System Error/Asynchronous Abort is pending by this mechanism.
The virtual System Error/Asynchronous Abort is enabled only when the HCR_EL2.AMO bit is
set.
VI, [7]
Virtual IRQ interrupt. The possible values are:
0 Virtual IRQ is not pending by this mechanism. This is the reset value.
1 Virtual IRQ is pending by this mechanism.
B2 AArch64 system registers
B2.48 Hypervisor Configuration Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-437
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