The virtual IRQ is enabled only when the HCR_EL2.IMO bit is set.
VF, [6]
Virtual FIQ interrupt. The possible values are:
0 Virtual FIQ is not pending by this mechanism. This is the reset value.
1 Virtual FIQ is pending by this mechanism.
The virtual FIQ is enabled only when the HCR_EL2.FMO bit is set.
AMO, [5]
Asynchronous abort and error interrupt routing. The possible values are:
0 Asynchronous external Aborts and SError Interrupts while executing at exception levels
lower than EL2 are not taken at EL2. Virtual System Error/Asynchronous Abort is disabled.
This is the reset value.
1 Asynchronous external Aborts and SError Interrupts while executing at EL2 or lower are
taken in EL2 unless routed by SCTLR_EL3.EA bit to EL3. Virtual System Error/
Asynchronous Abort is enabled.
IMO, [4]
Physical IRQ routing. The possible values are:
0 Physical IRQ while executing at exception levels lower than EL2 are not taken at EL2.
Virtual IRQ interrupt is disabled. This is the reset value.
1 Physical IRQ while executing at EL2 or lower are taken in EL2 unless routed by
SCTLR_EL3.IRQ bit to EL3. Virtual IRQ interrupt is enabled.
FMO, [3]
Physical FIQ routing. The possible values are:
0 Physical FIQ while executing at exception levels lower than EL2 are not taken at EL2.
Virtual FIQ interrupt is disabled. This is the reset value.
1 Physical FIQ while executing at EL2 or lower are taken in EL2 unless routed by
SCTLR_EL3.FIQ bit to EL3. Virtual FIQ interrupt is enabled.
PTW, [2]
Protected Table Walk. When this bit is set, if the stage 2 translation of a translation table access,
made as part of a stage 1 translation table walk at EL0 or EL1, maps to Device memory, the
access is faulted as a stage 2 Permission fault. The reset value is 0.
SWIO, [1]
Set/Way Invalidation Override. Non-secure EL1 execution of the data cache invalidate by
set/way instruction is treated as data cache clean and invalidate by set/way. When this bit is set:
• DCISW is treated as DCCISW when in the AArch32 Execution state.
• DC ISW is treated as DC CISW when in the AArch64 Execution state.
This bit is RES1.
VM, [0]
Enables second stage of translation. The possible values are:
0 Disables second stage translation. This is the reset value.
1 Enables second stage translation for execution in Non-secure EL1 and EL0.
To access the HCR_EL2:
MRS <Xt>, HCR_EL2 ; Read HCR_EL2 into Xt
MSR HCR_EL2, <Xt> ; Write Xt to HCR_EL2
B2 AArch64 system registers
B2.48 Hypervisor Configuration Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-438
Non-Confidential
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