WARMRSTREQ and DBGRSTREQ
The Armv8-A architecture provides a mechanism to configure whether a processor uses AArch32 or
AArch64 at EL3 as a result of a Warm reset. When the Reset Request bit in the RMR or RMR_EL3
register is set to 1, the processor asserts the WARMRSTREQ signal and the SoC reset controller can use
this request to trigger a Warm reset of the core and change the register width state. The AA64 bit in the
RMR or RMR_EL3 register selects the register width at the next Warm reset, at the highest Exception
level, EL3. An external debugger might also request a Warm reset of the core by asserting
DBGRSTREQ.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for information
about the recommended code sequence to use, to request a Warm reset.
You must apply steps 1 on page A4-65 to 6 on page A4-65 in the core powerdown sequence in
A4.6 Powering down an individual core on page A4-65, and wait until STANDBYWFI asserts
indicating the processor is idle, before asserting nCORERESET for that core. nCORERESET must
satisfy the timing requirements described in the Warm reset section.
A3 Clocks, Resets, and Input Synchronization
A3.3 Resets
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A3-55
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