Table A4-3 Supported processor power states (continued)
Power domains Description
PDMERCURY PDL2 PDCPU<n>
On Ret See Table A4-4 Supported core power states
on page A4-60
Processor on, L2 RAMs retained.
All cores either off or in WFx.
This is an L2 RAM retention entry or residency
condition.
On Ret See Table A4-4 Supported core power states
on page A4-60
Processor on, L2 RAMs retained.
At least one core running.
This is a transient condition.
On On See Table A4-4 Supported core power states
on page A4-60
Processor on, SCU/L2 RAMs active.
The following table describes the supported power domain states for individual cores. The power domain
state in each core is independent of all other cores.
Table A4-4 Supported core power states
Power domains Description
PDCPU PDADVSIMD
Off Off Core off.
On On Core on. Advanced SIMD and floating-point on.
On Ret AdvSIMD retention. Advanced SIMD and floating-point in retention.
Ret Ret Core retention. Core logic and Advanced SIMD and floating-point in retention.
You must follow the dynamic power management and powerup and powerdown sequences described in
the following sections. Any deviation from these sequences can lead to unpredictable results.
A4 Power Management
A4.1 Power domains
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A4-60
Non-Confidential
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