ARM Cortex-A35 User Manual

Table C10-2 PMU events (continued)
Bit Event number Event mnemonic Description
[18]
0x12
BR_PRED
Predictable branch speculatively executed:
1
This event is implemented.
[17]
0x11
CPU_CYCLES
Cycle:
1
This event is implemented.
[16]
0x10
BR_MIS_PRED
Mispredicted or not predicted branch speculatively executed:
1
This event is implemented.
[15]
0x0F
UNALIGNED_LDST_RETIRED
Instruction architecturally executed, condition check pass - unaligned load
or store:
1
This event is implemented.
[14]
0x0E
BR_RETURN_RETIRED
Instruction architecturally executed, condition check pass - procedure
return:
0
This event is not implemented.
[13]
0x0D
BR_IMMED_RETIRED
Instruction architecturally executed - immediate branch:
1
This event is implemented.
[12]
0x0C
PC_WRITE_RETIRED
Instruction architecturally executed, condition check pass - software
change of the PC:
1
This event is implemented.
[11]
0x0B
CID_WRITE_RETIRED
Instruction architecturally executed, condition check pass - write to
CONTEXTIDR:
1
This event is implemented.
[10]
0x0A
EXC_RETURN
Instruction architecturally executed, condition check pass - exception
return:
1
This event is implemented.
[9]
0x09
EXC_TAKEN
Exception taken:
1
This event is implemented.
[8]
0x08
INST_RETIRED
Instruction architecturally executed:
1
This event is implemented.
[7]
0x07
ST_RETIRED
Instruction architecturally executed, condition check pass - store:
1
This event is implemented.
[6]
0x06
LD_RETIRED
Instruction architecturally executed, condition check pass - load:
1
This event is implemented.
C10 PMU registers
C10.3 Performance Monitors Common Event Identification Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-697
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English