ARM Cortex-A35 User Manual

Table C10-2 PMU events (continued)
Bit Event number Event mnemonic Description
[5]
0x05
L1D_TLB_REFILL
L1 Data TLB refill:
1
This event is implemented.
[4]
0x04
L1D_CACHE
L1 Data cache access:
1
This event is implemented.
[3]
0x03
L1D_CACHE_REFILL
L1 Data cache refill:
1
This event is implemented.
[2]
0x02
L1I_TLB_REFILL
L1 Instruction TLB refill:
1
This event is implemented.
[1]
0x01
L1I_CACHE_REFILL
L1 Instruction cache refill:
1
This event is implemented.
[0]
0x00
SW_INCR
Instruction architecturally executed, condition check pass - software
increment:
1
This event is implemented.
To access the PMCEID0:
MRC p15,0,<Rt>,c9,c12,6 ; Read PMCEID0 into Rt
The PMCEID0 can be accessed through the external debug interface, offset 0xE20.
C10 PMU registers
C10.3 Performance Monitors Common Event Identification Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-698
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English