ARM Cortex-A35 User Manual

B1.66 Hyp IPA Fault Address Register .......................................................................... B1-253
B1.67 Hyp System Control Register .............................................................................. B1-254
B1.68 Hyp Syndrome Register ...................................................................................... B1-258
B1.69 Hyp System Trap Register .................................................................................. B1-259
B1.70 Hyp Translation Control Register ........................................................................ B1-263
B1.71 Hyp Vector Base Address Register .................................. .................................. B1-265
B1.72 Auxiliary Feature Register 0 ................................................................................ B1-266
B1.73 Debug Feature Register 0 ......................................... ......................................... B1-267
B1.74 Instruction Set Attribute Register 0 .................................. .................................. B1-269
B1.75 Instruction Set Attribute Register 1 .................................. .................................. B1-271
B1.76 Instruction Set Attribute Register 2 .................................. .................................. B1-273
B1.77 Instruction Set Attribute Register 3 .................................. .................................. B1-275
B1.78 Instruction Set Attribute Register 4 .................................. .................................. B1-277
B1.79 Instruction Set Attribute Register 5 .................................. .................................. B1-279
B1.80 Memory Model Feature Register 0 ...................................................................... B1-281
B1.81 Memory Model Feature Register 1 ...................................................................... B1-283
B1.82 Memory Model Feature Register 2 ...................................................................... B1-285
B1.83 Memory Model Feature Register 3 ...................................................................... B1-287
B1.84 Processor Feature Register 0 ...................................... ...................................... B1-289
B1.85 Processor Feature Register 1 ...................................... ...................................... B1-291
B1.86 Instruction Fault Address Register ...................................................................... B1-293
B1.87 Instruction Fault Status Register .................................... .................................... B1-294
B1.88 IFSR with Short-descriptor translation table format ...................... ...................... B1-295
B1.89 IFSR with Long-descriptor translation table format ...................... ...................... B1-297
B1.90 Interrupt Status Register .......................................... .......................................... B1-299
B1.91 L2 Auxiliary Control Register ....................................... ....................................... B1-301
B1.92 L2 Control Register .............................................. .............................................. B1-303
B1.93 L2 Extended Control Register ...................................... ...................................... B1-305
B1.94 L2 Memory Error Syndrome Register ................................ ................................ B1-307
B1.95 Memory Attribute Indirection Registers 0 and 1 .................................................. B1-310
B1.96 Main ID Register ................................................ ................................................ B1-313
B1.97 Multiprocessor Affinity Register ..................................... ..................................... B1-315
B1.98 Non-Secure Access Control Register ................................ ................................ B1-317
B1.99 Normal Memory Remap Register ........................................................................ B1-319
B1.100 Physical Address Register .................................................................................. B1-321
B1.101 Primary Region Remap Register .................................... .................................... B1-322
B1.102 Revision ID Register ............................................. ............................................. B1-325
B1.103 Reset Management Register .............................................................................. B1-326
B1.104 Secure Configuration Register ............................................................................ B1-328
B1.105 System Control Register .......................................... .......................................... B1-331
B1.106 Secure Debug Control Register .......................................................................... B1-335
B1.107 Secure Debug Enable Register ..................................... ..................................... B1-337
B1.108 TCM Type Register .............................................. .............................................. B1-339
B1.109 TLB Type Register ............................................... ............................................... B1-340
B1.110 Translation Table Base Control Register .............................. .............................. B1-341
B1.111 TTBCR with Short-descriptor translation table format .................... .................... B1-342
B1.112 TTBCR with Long-descriptor translation table format .................... .................... B1-343
B1.113 Translation Table Base Register 0 ...................................................................... B1-346
B1.114 TTBR0 with Short-descriptor translation table format .................... .................... B1-347
B1.115 TTBR0 with Long-descriptor translation table format .......................................... B1-349
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English