ARM Cortex-A35 User Manual

Table A-5 AXI4 Stream Protocol signals for messages from the Distributor to the GIC CPU Interface (continued)
Signal Direction Description
ICDTDATA[15:0] Input Primary payload for the data that is passing across the interface.
ICDTLAST Input Indicates the boundary of a packet.
ICDTDEST[1:0] Input Routing information for the data stream.
Table A-6 AXI4 Stream Protocol signals for messages from the GIC CPU Interface to the Distributor
Signal Direction Description
ICCTVALID Output Indicates that the master is driving a valid transfer.
ICCTREADY Input Indicates that the slave can accept a transfer in the current cycle.
ICCTDATA[15:0] Output Primary payload for the data that is passing across the interface.
ICCTLAST Output Indicates the boundary of a packet.
ICCTID[1:0] Output Data stream identifier.
Related information
B1.49 Data Fault Status Register on page B1-223
B2.41 Exception Syndrome Register, EL1 on page B2-423
B1.38 Configuration Base Address Register on page B1-200
Chapter A12 GIC CPU Interface on page A12-141
A Signal Descriptions
A.5 GIC signals
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English