ARM Cortex-A35

A.6 Generic Timer signals
The processor uses a standard set of signals for the Generic Timer.
Table A-7 Generic Timer signals
Signal Direction Description
nCNTHPIRQ[CN:0] Output Hypervisor physical timer event.
nCNTPNSIRQ[CN:0] Output Non-secure physical timer event.
nCNTPSIRQ[CN:0] Output Secure physical timer event.
nCNTVIRQ[CN:0] Output Virtual physical timer event.
CNTCLKEN Input
Counter clock enable.
This clock enable must be asserted one cycle before the CNTVALUEB bus.
CNTVALUEB[63:0] Input
Global system counter value in binary format.
Related information
A2.4 About the Generic Timer on page A2-47
A Signal Descriptions
A.6 Generic Timer signals
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