ARM Cortex-A35 User Manual

B2.92 System Control Register, EL3 ...................................... ...................................... B2-532
B2.93 Secure Debug Enable Register, EL3 .................................................................. B2-535
B2.94 Translation Control Register, EL1 ................................... ................................... B2-536
B2.95 Translation Control Register, EL2 ................................... ................................... B2-540
B2.96 Translation Control Register, EL3 ................................... ................................... B2-543
B2.97 Translation Table Base Register 0, EL1 .............................................................. B2-546
B2.98 Translation Table Base Register 1, EL1 .............................................................. B2-548
B2.99 Translation Table Base Register 0, EL3 .............................................................. B2-550
B2.100 Vector Base Address Register, EL1 .................................................................... B2-551
B2.101 Vector Base Address Register, EL2 .................................................................... B2-552
B2.102 Vector Base Address Register, EL3 .................................................................... B2-553
B2.103 Virtualization Multiprocessor ID Register, EL2 .................................................... B2-554
B2.104 Virtualization Processor ID Register, EL2 ............................. ............................. B2-555
B2.105 Virtualization Translation Control Register, EL2 .................................................. B2-556
Chapter B3 GIC registers
B3.1 CPU interface register summary .................................... .................................... B3-560
B3.2 Active Priority Register ........................................................................................ B3-561
B3.3 CPU Interface Identification Register .................................................................. B3-562
B3.4 Virtual interface control register summary ............................. ............................. B3-563
B3.5 VGIC Type Register ............................................................................................ B3-564
B3.6 Virtual CPU interface register summary .............................................................. B3-565
B3.7 VM Active Priority Register ........................................ ........................................ B3-566
B3.8 VM CPU Interface Identification Register ............................................................ B3-567
Chapter B4 Generic Timer registers
B4.1 Generic Timer register summary .................................... .................................... B4-570
B4.2 AArch32 Generic Timer register summary .......................................................... B4-571
B4.3 AArch64 Generic Timer register summary .......................................................... B4-572
Part C Debug
Chapter C1 Debug
C1.1 About debug methods ............................................ ............................................ C1-576
C1.2 Debug access .................................................. .................................................. C1-577
C1.3 Effects of resets on debug registers ................................. ................................. C1-578
C1.4 External access permissions to debug registers ........................ ........................ C1-579
C1.5 Debug events ...................................................................................................... C1-580
C1.6 Debug memory map ............................................. ............................................. C1-581
C1.7 Debug signals .................................................. .................................................. C1-583
C1.8 Changing the authentication signals for debug ......................... ......................... C1-584
Chapter C2 PMU
C2.1 About the PMU .................................................................................................... C2-586
C2.2 External register access permissions to the PMU registers ................................ C2-587
C2.3 Performance monitoring events .......................................................................... C2-588
C2.4 PMU interrupts .................................................................................................... C2-592
C2.5 Exporting PMU events ........................................................................................ C2-593
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English