B2.42 Exception Syndrome Register, EL2 .................................................................... B2-425
B2.43 Exception Syndrome Register, EL3 .................................................................... B2-427
B2.44 Fault Address Register, EL1 ....................................... ....................................... B2-429
B2.45 Fault Address Register, EL2 ....................................... ....................................... B2-430
B2.46 Fault Address Register, EL3 ....................................... ....................................... B2-431
B2.47 Hyp Auxiliary Configuration Register, EL2 .......................................................... B2-432
B2.48 Hypervisor Configuration Register, EL2 .............................................................. B2-433
B2.49 Hypervisor IPA Fault Address Register, EL2 ........................... ........................... B2-440
B2.50 Hyp System Trap Register, EL2 .......................................................................... B2-441
B2.51 AArch64 Debug Feature Register 0, EL1 ............................................................ B2-444
B2.52 AArch64 Instruction Set Attribute Register 0, EL1 .............................................. B2-446
B2.53 AArch64 Memory Model Feature Register 0, EL1 ....................... ....................... B2-448
B2.54 AArch64 Processor Feature Register 0, EL1 ...................................................... B2-450
B2.55 AArch32 Auxiliary Feature Register 0, EL1 ............................ ............................ B2-452
B2.56 AArch32 Debug Feature Register 0, EL1 ............................................................ B2-453
B2.57 AArch32 Instruction Set Attribute Register 0, EL1 .............................................. B2-455
B2.58 AArch32 Instruction Set Attribute Register 1, EL1 .............................................. B2-457
B2.59 AArch32 Instruction Set Attribute Register 2, EL1 .............................................. B2-459
B2.60 AArch32 Instruction Set Attribute Register 3, EL1 .............................................. B2-461
B2.61 AArch32 Instruction Set Attribute Register 4, EL1 .............................................. B2-463
B2.62 AArch32 Instruction Set Attribute Register 5, EL1 .............................................. B2-465
B2.63 AArch32 Memory Model Feature Register 0, EL1 ....................... ....................... B2-467
B2.64 AArch32 Memory Model Feature Register 1, EL1 ....................... ....................... B2-469
B2.65 AArch32 Memory Model Feature Register 2, EL1 ....................... ....................... B2-471
B2.66 AArch32 Memory Model Feature Register 3, EL1 ....................... ....................... B2-473
B2.67 AArch32 Processor Feature Register 0, EL1 ...................................................... B2-475
B2.68 AArch32 Processor Feature Register 1, EL1 ...................................................... B2-477
B2.69 Instruction Fault Status Register, EL2 ................................ ................................ B2-479
B2.70 IFSR32_EL2 with Short-descriptor translation table format ................................ B2-480
B2.71 IFSR32_EL2 with Long-descriptor translation table format ................ ................ B2-482
B2.72 Interrupt Status Register, EL1 ...................................... ...................................... B2-484
B2.73 L2 Auxiliary Control Register, EL1 ...................................................................... B2-486
B2.74 L2 Control Register, EL1 .......................................... .......................................... B2-489
B2.75 L2 Extended Control Register, EL1 .................................. .................................. B2-491
B2.76 L2 Memory Error Syndrome Register, EL1 ............................ ............................ B2-493
B2.77 Memory Attribute Indirection Register, EL1 ............................ ............................ B2-496
B2.78 Memory Attribute Indirection Register, EL2 ............................ ............................ B2-498
B2.79 Memory Attribute Indirection Register, EL3 ............................ ............................ B2-499
B2.80 Monitor Debug Configuration Register, EL2 ........................................................ B2-500
B2.81 Monitor Debug Configuration Register, EL3 ........................................................ B2-503
B2.82 Monitor Debug System Control Register, EL1 .................................................... B2-506
B2.83 Main ID Register, EL1 ............................................ ............................................ B2-510
B2.84 Multiprocessor Affinity Register, EL1 .................................................................. B2-512
B2.85 Physical Address Register, EL1 .......................................................................... B2-514
B2.86 Revision ID Register, EL1 ......................................... ......................................... B2-518
B2.87 Reset Management Register, EL3 ...................................................................... B2-519
B2.88 Reset Vector Base Address Register, EL3 .......................................................... B2-521
B2.89 Secure Configuration Register, EL3 .................................................................... B2-522
B2.90 System Control Register, EL1 ...................................... ...................................... B2-525
B2.91 System Control Register, EL2 ...................................... ...................................... B2-529
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
11
Non-Confidential
To Next Page
Loading...
Need help?
General
