ARM Cortex-A35 User Manual

Table A10-3 Attributes of the CHI master memory interface (continued)
Attribute Value Comments
Transaction ID
width
8 The ID encodes the source of the memory transaction. See A9.5 Attributes of the ACE
master interface on page A9-120.
Transaction ID
capability
8n + 4m + w + 1 8 for each core in the cluster in addition to:
• 4 for the ACP interface.
• 1 for barriers.
• 6 to 11 writes, depending on the write issuing capability.
Unlike in configurations with AXI or ACE, there is never any ID reuse in CHI
implementations, regardless of the memory type.
There is no fixed mapping between CHI transaction IDs and cores. Some transaction IDs can be used for
either reads or writes.
Related information
A9.5 Attributes of the ACE master interface on page A9-120
Arm® AMBA® 5 CHI Protocol Specification
A10 CHI Master Interface
A10.3 Attributes of the CHI master interface
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
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A10-129
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English