ARM Cortex-A35

Table B1-19 Identification registers (continued)
Name CRn Op1 CRm Op2 Reset Description
ID_ISAR5 c0 0 c2 5
0x00011121
B1.79 Instruction Set Attribute Register 5 on page B1-279
ID_ISAR5 has the value 0x00010001 if the Cryptographic Extension is not
implemented and enabled.
CCSIDR 1 c0 0 -
B1.39 Cache Size ID Register on page B1-201
CLIDR 1
0x0A200023
B1.40 Cache Level ID Register on page B1-204
The value is 0x09200003 if the L2 cache is not implemented.
AIDR 7
0x00000000
B1.34 Auxiliary ID Register on page B1-196
CSSELR 2 c0 0
0x00000000
B1.45 Cache Size Selection Register on page B1-217
B1 AArch32 system registers
B1.20 AArch32 Identification registers
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B1-177
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