ARM Cortex-A35

Table B1-28 AArch32 GIC system registers (continued)
Name CRn Op1 CRm Op2 Type Reset Width Description
ICH_EISR c12 4 c8 3 RO
0x00000000
32-bit Interrupt Controller End of Interrupt Status Register
ICH_VMCR 7 RW
0x004C0000
32-bit Interrupt Controller Virtual Machine Control Register
ICH_ELRSR 5 RO
0x0000000F
32-bit Interrupt Controller Empty List Register Status Register
ICH_LR0 c12 0 RW
0x00000000
32-bit Interrupt Controller List Register 0
ICH_LR1 1 RW
0x00000000
32-bit Interrupt Controller List Register 1
ICH_LR2 2 RW
0x00000000
32-bit Interrupt Controller List Register 2
ICH_LR3 3 RW
0x00000000
32-bit Interrupt Controller List Register 3
ICH_LRC0 c14 0 RW
0x00000000
32-bit Interrupt Controller List Register 0
ICH_LRC1 1 RW
0x00000000
32-bit Interrupt Controller List Register 1
ICH_LRC2 2 RW
0x00000000
32-bit Interrupt Controller List Register 2
ICH_LRC3 3 RW
0x00000000
32-bit Interrupt Controller List Register 3
ICC_MCTLR 6 c12 4 RW
0x00000400
32-bit Interrupt Control Register for EL3
ICC_MSRE 5 RW
0x00000000
32-bit System Register Enable Register for EL3
ICC_MGRPEN1 7 RW
0x00000000
32-bit Interrupt Controller Monitor Interrupt Group 1 Enable
register
B1 AArch32 system registers
B1.29 AArch32 GIC system registers
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