L1 Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction
cache:
0b10 Virtually Indexed Physically Tagged (VIPT).
[13:4]
Reserved, RES0.
IminLine, [3:0]
Log
2
of the number of words in the smallest cache line of all the instruction caches that the
processor controls.
0x4 Smallest instruction cache line size is 16 words.
To access the CTR:
MRC p15,0,<Rt>,c0,c0,1 ; Read CTR into Rt
Register access is encoded as follows:
Table B1-40 CTR access encoding
coproc opc1 CRn CRm opc2
1111 010 0000 0000 001
B1 AArch32 system registers
B1.46 Cache Type Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-220
Non-Confidential
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