0 Secure access only. Any attempt to access CP11 in Non-secure state results in an Undefined
Instruction exception. If the processor is in Non-secure state, the corresponding bits in the
CPACR ignore writes and read as 0b00, access denied. This is the reset value.
1 Secure or Non-secure access.
If Advanced SIMD and Floating-point are not implemented, this bit is RES0.
cp10, [10]
Non-secure access to CP10 enable:
0 Secure access only. Any attempt to access CP10 in Non-secure state results in an Undefined
Instruction exception. If the processor is in Non-secure state, the corresponding bits in the
CPACR ignore writes and read as 0b00, access denied. This is the reset value.
1 Secure or Non-secure access.
If Advanced SIMD and floating-point are not implemented, this bit is RES0.
[9:0]
Reserved, RES0.
If the CP11 and CP10 fields are set to different values, the behavior is CONSTRAINED
UNPREDICTABLE. It is the same as if both fields were set to the value of CP10, in all respects other
than the value read back by explicitly reading CP11.
To access the NSACR:
MRC p15, 0, <Rt>, c1, c1, 2 ; Read NSACR into Rt
MCR p15, 0, <Rt>, c1, c1, 2 ; Write Rt to NSACR
Register access is encoded as follows:
Table B1-83 NSACR access encoding
coproc opc1 CRn CRm opc2
1111 000 0001 0001 010
B1 AArch32 system registers
B1.98 Non-Secure Access Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-318
Non-Confidential
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