ARM Cortex-A35 User Manual

1 Executes data cache clean operations as data cache clean and invalidate. The following
operations are affected:
• In AArch32, DCCSW is executed as DCCISW, DCCMVAU and DCCMVAC are
executed as DCCIMVAC.
• In AArch64, DC CSW is executed as DC CISW, DC CVAU and DC CVAC are
executed as DC CIVAC.
[43:31]
Reserved, RES0.
CDIDIS, [30]
Disable Cryptographic dual issue. The possible values are:
0 Enable dual issue of floating-point, Advanced SIMD and Cryptographic instructions.
This is the reset value.
1 Disable dual issue of floating-point, Advanced SIMD and Cryptographic instructions.
DIDIS, [29]
Disable Dual Issue. The possible values are:
0 Enable Dual Issue of instructions. This is the reset value.
1 Disable Dual Issue of all instructions.
RADIS, [28:27]
Write streaming no-allocate threshold. The possible values are:
0b00 16th consecutive streaming cache line does not allocate in the L1 or L2 cache.
0b01 128th consecutive streaming cache line does not allocate in the L1 or L2 cache. This is
the reset value.
0b10 512th consecutive streaming cache line does not allocate in the L1 or L2 cache.
0b11 Disables streaming. All write-allocate lines allocate in the L1 or L2 cache.
L1RADIS, [26:25]
Write streaming no-L1-allocate threshold. The possible values are:
0b00 4th consecutive streaming cache line does not allocate in the L1 cache. This is the
reset value.
0b01 64th consecutive streaming cache line does not allocate in the L1 cache.
0b10 128th consecutive streaming cache line does not allocate in the L1 cache.
0b11 Disables streaming. All write-allocate lines allocate in the L1 cache.
DTAH, [24]
Disable transient and no-read-allocate hints for loads. The possible values are:
0 Normal operation.
1 Transient and no-read-allocate hints in the MAIR are ignored and treated the same as
non-transient, read-allocate types for loads. The LDNP instruction in AArch64 behaves
the same as the equivalent LDP instruction. This is the reset value.
STBPFRS, [23]
Disable ReadUnique request for prefetch streams initiated by STB accesses:
0 ReadUnique used for prefetch streams initiated from STB accesses. This is the reset
value.
1 ReadShared used for prefetch streams initiated from STB accesses.
B2 AArch64 system registers
B2.36 CPU Auxiliary Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-413
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English